Ir. Dr. Nurul Hazlina Noordin

1. 1. 1. Module 1: Fundamentals of IC and HDL Design This module lays the groundwork.
         • You will explore the digital design abstraction hierarchy—from behavioral down to physical implementation levels.
         • You will be introduced to Hardware Description Languages (HDL), specifically Verilog, learning its syntax and various modeling styles (structural, dataflow, and behavioral).
         • Most importantly, you will learn how to verify your digital circuits before touching any hardware by constructing testbenches and performing functional simulations using ModelSim.
      2. Module 2: RTL Design and Synthesis Once you know how to write and simulate Verilog, Module 2 focuses on transformation.
         • You will learn how Register Transfer Level (RTL) designs are synthesized into actual hardware components.
         • We will explore technology mapping and gate-level netlist generation using Intel Quartus Prime tools, teaching you how to analyze compilation reports and evaluate resource utilization.
      3. Module 3: Timing Analysis and Design Optimization Synthesizing code into gates is only half the battle; the hardware must also run at the correct speed.
         • This final module emphasizes practical hardware deployment on the Altera DE10-Lite FPGA board.
         • You will dive into Static Timing Analysis (STA), learning about critical paths, setup and hold times, and slack.
         • You will also apply optimization techniques like pipelining to hit timing closure before presenting your final capstone project.

1. 1. The Evolution of Logic Devices
      • Before modern FPGAs (Field-Programmable Gate Arrays) dominated the market, engineers relied on older programmable logic devices.
      • We start by gaining a historical perspective on the evolution from early PLAs (Programmable Logic Arrays), PALs (Programmable Array Logic), and PLDs (Programmable Logic Devices) to the highly advanced FPGA systems we use today.   
   2. FPGAs vs. Microcontrollers vs. ASICs
      • Why use an FPGA? We compare FPGAs against standard Microcontrollers (MCUs) and Application-Specific Integrated Circuits (ASICs).
        1. Microcontrollers execute instructions sequentially and have fixed architectures, making them great for embedded control but slower for massive computations.
        2. ASICs are highly optimized for specific tasks and boast high performance, but they are expensive to develop and their hardware cannot be changed once fabricated.
        3. FPGAs offer the best of both worlds: they provide high parallel processing power and are highly reconfigurable, meaning you can reprogram their internal logic to suit different designs at a moderate cost.

3. Design Abstraction Levels

Modern digital design is too complex to build gate-by-gate. Instead, we use different abstraction levels to manage complexity:

• • • Behavioral Modeling

Describes the algorithm or behavior using high-level programming constructs (like if-else and case statements).

• • • Dataflow Modeling

Describes how data moves through the circuit using Boolean expressions and continuous assignments.

• • • Structural Modeling (Gate-Level)

Explicitly describes how individual components and logic gates are wired together physically.

4. The FPGA Design Flow

Bringing a digital concept to life requires a strict engineering workflow. This week, we cover the general steps you will repeat throughout the semester:

1. 1. 1. Design Entry
         • Writing your Verilog HDL code to describe the circuit.
      2. Synthesis
         • The Quartus software translates your high-level HDL into a gate-level netlist, optimizing the logic and mapping it to the FPGA’s specific resources (like Look-Up Tables and Flip-Flops).
      3. Implementation
         • The software physically places the logic blocks on the FPGA chip and routes the microscopic wires between them.
      4. Timing Analysis
         • Checking to ensure the physical routing delays don’t violate strict timing rules (setup and hold times).
      5. Bitstream Generation
         • Generating a .sof binary configuration file that gets downloaded to the FPGA to physically program it.