Author: hazlina

Reimagining the Engineering Classroom: New Collection on GenAI and the Cognitive Learning Curve

260701 – Discover Education eFlyer_Reimagining Engineering Pedagogy Balancing Cognitive Development and Generative AI in Computational Learning

When Springer Nature first approached me to submit a proposal for a new journal collection, it happened to be Week 5 of the lecture semester. As I stood in front of my class, a realization crossed my mind about how much the landscape of teaching has shifted.

Today’s students have an incredible wealth of resources right at their fingertips. With the rise of Generative AI (GenAI), sourcing facts, generating code, or finding answers is no longer a challenge. Information is practically instantaneous.

But as educators, we face a dilemma – well, at least, I do.

You can ask AI to generate an answer, but you cannot outsource “understanding.” True understanding is an internal, deeply personal cognitive process. It is that suara hati (the inner voice) where a student rationalizes a problem, wrestles with the logic, and finally externalizes it by explaining or applying it.

In engineering education, where technological breakthroughs move at breakneck speed, simply banning or restricting AI in the classroom is an outdated approach. Yet, granting unfettered access without a proper pedagogical framework presents a dangerous risk: it dilutes the actual human learning curve and breeds cognitive dependency. How do we ensure our future engineers are still learning how to think, not just how to prompt?

Driven by this exact tension, I submitted a proposal that was recently accepted by Springer Nature’s Discover Education journal: “Reimagining Engineering Pedagogy: Balancing Cognitive Development and Generative AI in Computational Learning.” 🙂

The ultimate aim of this collection is to create a collaborative space where we can learn from best practices, empirical observations, and innovative frameworks developed by educators across the global engineering segment. We want to uncover how to design learning environments where GenAI acts as a technical accelerant without bypassing the essential human cognitive processing required for true mastery.

Join the Conversation & Submit Your Work

To all fellow engineering educators, researchers, and practitioners out there: if you are actively navigating this paradigm shift in your classrooms—whether in electrical, mechanical, civil, chemical, or software engineering—I warmly invite you to submit your research, case studies, or conceptual frameworks to this collection.

Let’s work together to shape the future of how engineering is taught.

View the official collection webpage and submission guidelines here: Click here to view the Collection Webpage

Note: The official Call for Papers document containing the detailed scope and submission timelines is attached below/on the website for your reference. Please feel free to reshare this call within your academic networks! Looking forward to your valuable submissions.

Raspberry Programming 2026/4 – MRSM Transkrian

*UMPSA STEM Lab Raspberry Pi Programming Synopsis can be found here.

In the Raspberry Pi IoT session, 36 students and teachers from MRSM Transkrian were introduced to the concept of the Internet of Things (IoT) using Raspberry Pi on the UMP STEM Cube, a pico-satellite learning kit specifically designed to facilitate engineering learning.

The content covered basic digital input/output operations on onboard LEDs, as well as topics such as dashboard design using gyro meter and BMU280 sensor data, including collecting and storing data in a cloud database. Participants learned to interface sensors with Raspberry Pi boards and develop IoT applications for real-world scenarios. The session provided students with valuable insights into IoT technology and its applications in various domains.

A special appreciation is extended to Cikgu Mohamad from MRSM Transkrian for coordination in facilitating communication between the participants and the UMPSA STEM Lab :).

Nurul June 24th

 

BHE3233 BTE4433 – Week 14 Lab Submission

BHE3233

Group 1 – AES

Group 2 – FIR Filter

Group 3 – FIR Filter

BTS4433

https://www.youtube.com/shorts/xrJ00I3LIlE

Group 2

Group 5

Group 8

Group 5

https://www.youtube.com/shorts/royQgfZswWc

https://www.youtube.com/shorts/QMlo0IBENTA

Group 1

https://www.youtube.com/shorts/e9hTOs6n7F8?si=F-tFTJrBuzMDtV41

Group 2

https://www.youtube.com/shorts/wrp0cACEB4k

Group 7

BHE3233 BTE4433 – Week 13 Project Presentation

What an incredible journey it has been! This week is the presentations week for the BHE3233 and BTS4433 cohorts. After weeks of development through our tiered scaffolding approach—moving from Stage 1 (Workout Programming) to Stage 4 (Comparative Optimization)—every student successfully presented their hardware architectures.

Watching everyone dissect, design, and compare four distinct digital systems was a proud moment for the UMPSA STEM Lab. But how exactly do these projects tie into our overall syllabus, and how have they built the critical Verilog coding criteria our students will take into the industry?

Let’s break it down.

The Projects: Four Pillars of Digital System Design
The course syllabus was intentionally structured to expose students to four highly distinct industry domains. By encouragung students to design and then optimize each of these systems, the syllabus ensured a comprehensive grasp of real-world hardware challenges:

  1. Project 1: Cryptography (Security-Focused): Students dove into hardware encryption by designing an 8-bit AES S-Box. By Stage 4, they compared a memory-heavy Look-Up Table (LUT) approach against an area-efficient Logic-based (Boolean/Galois Field) approach, learning how to select architectures based on whether they are building a high-speed processor or a low-area IoT device.
  2. Project 2: CPU / ALU Design (Arithmetic-Focused): Escalating a basic multiplier to 16-bit logic, students had to evaluate complex mathematical trees. They compared Behavioral, Sequential (Shift-and-Add), and Pipelined multipliers. This taught them the delicate balance between saving Logic Elements (LEs) for handheld devices versus maximizing throughput for heavy computation.
  3. Project 3: DSP & Sensor Processing: Students built a 4-tap FIR filter, calculating precise bit-widths to prevent arithmetic overflow. The final optimization challenged them to shift from a Direct Form to a Transposed Form architecture, proving that mathematically identical Verilog code can yield vastly different Max Frequencies (fMAX) simply by shortening the critical path.
  4. Project 4: Communication Protocols (Interfacing): Focusing on high-reliability data transmission, students built a UART Controller with an integrated Baud Rate Generator and Parity checking. By comparing Binary-Encoded FSMs against One-Hot Encoded FSMs, they learned how Verilog state machine encoding directly impacts flip-flop utilization and setup slack.

Building Verilog Criteria: Beyond Syntax
The most valuable outcome of this class is how it transformed the students’ Verilog coding criteria. The tiered scaffolding intentionally guided them through a specific evolutionary process:

  1. Code Comprehension & Hardware Inference (Stage 1): Students learned that Verilog isn’t just software code; it is a description of physical hardware. They learned how a simple * operator is interpreted by the Quartus synthesis engine.
  2. Debugging Hardware Logic (Stage 2): They learned to identify hardware-specific malfunctions, such as standard compliance errors (“Output port has no driver”) and catastrophic “Race Conditions” caused by using blocking assignments (=) instead of non-blocking assignments (<=) in sequential logic.
  3. Architectural Integration (Stage 3): They learned how to connect verified sub-modules into complex top-level architectures, carefully calculating bit-growth across the data path.
  4. Scientific Optimization (Stage 4): This is where they built their highest-level Verilog criteria. They learned to rely on the Quartus TimeQuest Timing Analyzer and Resource Utilization reports to justify their designs, comparing Total Logic Elements, Registers, Max Frequency (fMAX), and Latency.

Preparing for the Engineering Tasks
As noted in the course materials, escalating designs to handle complex optimizations moves a student from simply “making things work” to “optimizing things for performance,” which is the hallmark of a true Digital Design Engineer.

Congratulations to all the BHE3233 and BTS4433 students! You didn’t just write Verilog this semester; you intelligently traded Area for Speed, evaluated critical paths, and solved complex timing puzzles. You are now fully equipped to tackle modern FPGA and ASIC design challenges in the industry!