Tag: Academia – ESD

BHE3233 BTS4433 – Week 7 – Sequential RTL – Lab 4

Welcome to Week 7! This week, we took a massive leap in our digital design journey by exploring Register Transfer Level (RTL) sequential circuits. Unlike combinational circuits, sequential circuits have memory, meaning their outputs depend not only on current inputs but also on previous input
history. At the heart of these sequential designs is the Finite State Machine (FSM).
In digital design, FSMs are used to control system behavior by transitioning between a finite number of states based on inputs and clock cycles.
When we build FSMs in Verilog, we generally divide the architecture into three main blocks:
        1. The State Register: This is a synchronous block (using always @(posedge clk)) that updates the current state to the next state at every clock edge, or resets it when a reset signal is triggered.
        2. The Next-State Logic: A combinational block that evaluates the current state and external inputs to determine what the next state should be.
        3. The Output Logic: A combinational block that generates the output signals based on the current state (Moore machine) or both the current state and inputs (Mealy machine).
In class, we looked at a practical example: a sequence detector acting as a lock that opens whenever the serial bit pattern “1011” is achieved.
Before writing any Verilog code, it is incredibly important to derive your state machine on pen and paper first. Drawing an abstract state diagram ensures your states and transition logic actually make sense.
For the “1011” detector, our state diagram tracks how much of the pattern we have seen so far:
        1. S0: Nothing matched yet.
        2. S1: Matched “1”.
        3. S2: Matched “10”
        4. S3: Matched “101”
        5. S4: Matched the full “1011” sequence (this is where the output goes high).
By mapping out the transition arrows—such as moving from S1 to S2 if the input is 0, or dropping back to S0 if the sequence is broken—you establish the exact mathematical behavior your next-state logic block needs to model.
Hands-On: Lab 4 and the Satellite Communication System
Once we nailed down the state diagrams on paper, we moved into the hardware phase with Lab 4: Finite State Machine for Satellite Communication Link
In real picosatellite systems, communication links require a strict, multi-stage initialization and termination process . You simulated this exact scenario using a four-state FSM:
      1. IDLE: Waiting for the start command.
      2. LINK_ESTABLISH: Attempting the communication handshake.
      3. DATA_TRANSFER: The active data transmission session
      4. LINK_TERMINATE: Securely closing the session 
During the lab, you mapped your DE10-Lite board’s switches to act as the transition triggers (e.g., SW0 to start communication, SW1 to signify link established) and used the LEDs to track which state the FSM was currently in.
By verifying the state transitions in a ModelSim simulation and testing it directly on the physical board, you successfully built a control system identical to those used in real-time embedded space missions !
Keep practicing drawing those state diagrams on paper before jumping into Quartus. See you next week!

 

2026 Book :) Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis

The book is finally in =).

There is a specific kind of satisfaction in hardware engineering—the moment a conceptual logic circuit transitions from a schematic to a functional physical implementation. My fascination with this process began in 1999 during my undergraduate studies under Professor Othman Sidek. Back then, the ability of an FPGA to house a vast array of logic functions felt revolutionary.

It all started with a project in my Digital Electronics 2 subject. I remember it vividly, we built an automated counter for badminton matches. The digital logic system was designed to detect whether a shuttlecock landed in or out of bounds to assist the umpire in ruling points. That small-scale project served as the gateway to a much deeper exploration into digital systems.

From Undergraduate Roots to GSM Architecture

By the time I reached my final year project, I was diving deep into digital systems for GSM communication modules. Through a family connection—my cousin, who was then a technician for a leading telecommunications provider—I gained invaluable access to the industry standards of the time.

I was particularly focused on implementing Convolutional Encoders, which were essential for error correction in mobile networks. At the time, we worked across the five primary channel types:

      1. TCH/FS (Full Rate Speech)

      2. TCH/HS (Half Rate Speech)

      3. FACCH (Fast Associated Control Channel)

      4. SACCH (Slow Associated Control Channel)

      5. SDCCH (Standalone Dedicated Control Channel)

The successful implementation of these designs wasn’t just a hurdle to pass for graduation, it was the foundation of my continued passion with digital logic =p

Fast forward to 2021, I returned to the classroom to teach Digital System Design. Re-engaging with the subject after years in the field felt like a homecoming. During this period, I began supervising Phuah Soon Eu on the project involving the implementation of metaheuristic algorithms on IC chips.

The inherent challenges of translating high-level algorithms into hardware were tackled: managing floating-point arithmetic, optimizing RAM architectures, and modifying algorithmic flows to suit the rigid requirements of digital implementation.

Introducing the Book: A Practical Path for the Novice

Through the project implementation, a persistent “missing link” in technical FPGA education literature. There is a steep cliff between learning basic Verilog and understanding the professional constraints of a production-ready FPGA design.

To bridge this gap, this book is introduced.

Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis

The philosophy is simple: The best way to learn a system is to build it. We designed this text to guide the reader through three critical phases:

      1. Foundations: Introduction to FPGA architecture and Hardware Description Language (HDL).

      2. Synthesis: A deep dive into RTL modeling and the complexities of Static Timing Analysis (STA).

      3. Implementation: Mastering FPGA-specific design and the art of optimization.

Moving from Functional to Professional

This book is specifically written for those at the “Novice to Early-Intermediate” stage. It is for the designer to learn to perform a functional simulation but needs to learn how to read synthesis reports, meet specific timing targets, and redesign circuits with objective-driven outcomes.

It has been a privilege to author this with Phuah Soon Eu, and we hope this work serves as a catalyst for the next generation of digital designers—much like a badminton counter did for me decades ago :).

BHE3233 BTS4433 – Week 6 – FPGA Implementation of Combinational RTL – Lab 3

This week, we continued our exploration of combinatorial circuits, focusing on Lab 3 (Session 5): Implementation and Comparison of Ripple Carry Adder (RCA) and Carry Look-Ahead Adder (CLA). This lab builds on students’ foundational understanding of digital logic and provides hands-on experience with adder architectures that are central to arithmetic logic units (ALUs).

Lab Objectives

The key objectives of this lab were to:

      1. Design and implement 4-bit Ripple Carry Adders (RCA) and 4-bit Carry Look-Ahead Adders (CLA)
      2. Perform functional verification using selected test vectors
      3. Implement both designs on an FPGA platform
      4. Analyze and compare post-implementation parameters using Quartus post-implementation reports
      5. Introduce basic ALU functionality, focusing on multiplexing using case statements and transitioning toward decoder-based designs

Adder Design and Implementation

Students designed both adders using structural and behavioral modeling approaches in HDL:

  • Ripple Carry Adder (RCA):
    A straightforward adder where each full adder waits for the carry from the previous stage. This simplicity comes at the cost of increased propagation delay.
  • Carry Look-Ahead Adder (CLA):
    A faster alternative that computes carry signals in parallel using generate and propagate logic, significantly reducing carry propagation delay.

Both designs were synthesized and deployed on the FPGA to observe real hardware performance, not just simulation results.

Functional Testing

During functional testing, several input combinations were validated to ensure correctness:

      • A = 5 (0101), B = 3 (0011)
        • Result: 8 (1000)
        • Verified correct operation for both RCA and CLA.

      • A = 15 (1111), B = 1 (0001)
        • Result: 0 with carry-out = 1
        • This test demonstrated carry spill-over, confirming correct handling of overflow conditions.

These cases helped reinforce how carry propagation affects outputs and highlighted the functional equivalence of RCA and CLA despite architectural differences.

 

Post-Implementation Analysis (Quartus)

An important part of this lab was analyzing the post-implementation reports in Quartus.

 

Students were tasked with extracting and comparing the following parameters for both adder implementations:

        • Logic Elements (LEs) Used
          How much FPGA hardware is consumed by RCA versus CLA.
        • Combinational Functions
          Insight into the complexity of logic synthesized by the toolchain.
        • Maximum Clock Frequency (Fmax)
          The highest achievable clock rate based on timing constraints.
        • Critical Path Delay
          The longest combinational delay path, which is especially important when comparing RCA and CLA performance.

As expected, the RCA generally exhibited a longer critical path delay due to serial carry propagation, while the CLA achieved a higher maximum clock frequency, demonstrating its advantage in speed-critical designs.

In digital circuits, Fmax (maximum clock frequency) tells us how fast a circuit can run when a clock is used. It depends on the critical path, which is the longest delay through the combinational logic. Signals must be able to travel along this path and settle before the next clock edge arrives. If the critical path is long, the circuit needs a slower clock. In this lab, the RCA has a longer critical path because the carry must pass through each bit one by one, while the CLA reduces delay by calculating carries in parallel.

When checking the Quartus Timing Analysis Report, students noticed that it shows “No Fmax” and “No clock properties to report.” This is normal for this lab. Both the RCA and CLA designs are purely combinational and do not include any clocked elements such as flip-flops or registers. Since there is no clock defined in the design, Quartus cannot calculate Fmax. Fmax is only reported for sequential circuits where data moves from one register to another using a clock. For this reason, Quartus only reports logic usage and combinational delay. Once registers are added in future labs—such as in a registered ALU or datapath—Fmax and full timing information will become available.

To clearly observe the difference in hardware utilization, the total number of logic gates and Configurable Logic Elements (CLEs) used in the system can be analyzed by implementing both a 32-bit Carry Look-Ahead Adder (CLA) and a 32-bit Ripple Carry Adder (RCA). By experimenting with these two adders under identical design conditions, a direct comparison can be made. This allows the differences in resource usage to be clearly identified, where the CLA generally requires more gates and CLEs due to its complex carry logic, while the RCA uses fewer resources but operates with a longer propagation delay.

The example design above employs a genvar as a compile-time counter within a Verilog generate loop to create the 32 stages of the ripple carry adder. The counter variable i controls the instantiation of each full adder, where A[i] and B[i] represent the operand bits at position i, and carry[i] and carry[i+1] form the carry chain between adjacent stages. This approach improves scalability and code modularity, allowing the adder width to be easily adjusted without altering the underlying architecture. Importantly, the use of a counter does not affect the synthesized hardware, as the loop is unrolled during synthesis.

Introduction to Basic ALU Concepts

In the latter part of the lab, we began transitioning from simple adders to basic ALU design concepts:

      1. Students implemented a simple ALU capable of performing multiple operations.
      2. A case statement was used to implement a multiplexer that selects the desired operation based on an opcode.
      3. This approach helped students understand how operation selection works internally within an ALU.

We also discussed the next step in this progression: moving from case-based multiplexing toward decoder-based control logic, which scales better for more complex ALU designs.

You can also take this up a level by having your ALU with output assigned to 7 segment display:-

 

Key Takeaways

By the end of this lab, you should be able to:

      1. Understand the architectural and performance differences between RCA and CLA
      2. Validate combinational circuits through simulation and FPGA implementation
      3. Interpret FPGA post-implementation reports to justify design trade-offs
      4. See how simple adders evolve into more complex building blocks, such as ALUs

This lab serves as a crucial bridge between basic combinational logic and more advanced processor datapath components, setting the stage for upcoming topics in sequential logic and CPU design.

BHE3233 BTS4433 – Week 5 – FPGA Implementation of Combinational RTL

This week is important as we move from theoretical concepts to hands-on hardware implementation. You will be tackling Pre-Labs (Sessions 1 & 2) and Labs 1 & 2 (Sessions 3 & 4).

To succeed in this course and meet our core learning outcomes—specifically CO3, which focuses on developing FPGA designs using industry best practices—you must follow a structured approach.

Phase 1: The Foundation (Pre-Lab Sessions 1 & 2)

Before touching the hardware, you must set up your digital environment. These sessions focus on Project Setup and Functional Verification.

      • Software Installation: Ensure you have Intel Quartus Prime Lite Edition (Version 18.1) and ModelSim installed on your computer.

      • Project Creation: Launch the New Project Wizard in Quartus. Critical step: You must target the specific FPGA device on our board: MAX 10 – 10M50DAF484C7G.

  

      • Functional Simulation: Use ModelSim to verify your logic before synthesis. This allows you to catch bugs in a software environment where signals are easy to trace.

Phase 2: Hands-On Implementation (Labs 1 & 2)

Now, it’s time to bring your code to life on the DE10-Lite FPGA Board.

Lab 1: Blinking LEDs (Session 3)

In this lab, you will learn to control the board’s ten user-defined LEDs.

      • The Logic: You will write a Verilog module utilizing a counter to create a delay.

      • Key Tip: Remember that the onboard clock runs at 50 MHz. Your counter must be large enough (at least 25 bits) to create a blink visible to the human eye.

Lab 2: Switch Inputs and Debouncing (Session 4)

Mechanical switches are “noisy.” When you flip a switch, the signal “bounces” rapidly between high and low before settling.

  • The Challenge: You will implement Debounce Logic using a counter to ensure the FPGA only registers a clean, stable signal.

  • The Goal: Observe the difference between a direct switch-to-LED connection and one filtered through your debounce logic.

    How to Complete Your Lab Answer Sheets

Your lab worksheet is your evidence of learning. To receive full marks and satisfy CO3 requirements, every session entry must include:

  1. Unique Module Naming: To ensure individual work, you must prefix your top-level modules with your unique initials (e.g., AZ_LED_Blinking). Generic names will result in mark deductions.

  2. Verilog Code Snippets: Paste snapshots of your design module and your testbench.

  3. Simulation Waveforms: Provide ModelSim screenshots. Don’t just paste the image; add notes explaining the logic proof and calculating the clock cycles or frequency observed.

  4. Implementation Reports: After compiling in Quartus, open the Compilation Report. You must include snapshots showing Resource Utilization (how many LUTs and Registers your design used).

    Final Submission Reminder

Once you have completed all activities and filled out your worksheet for Sessions 1 through 4:

  1. Verify that all dates are recorded correctly.

  2. Ensure every module name is unique to you / your team member.

  3. Upload the completed document to KALAM (after Lab 6 – Session 8).

Success in digital design comes from attention to detail. Double-check your pin assignments in the Pin Planner before programming, and always verify your timing slack in the Summary Report.

For those who are interested to explore more about Pin Planner, do explore this YouTube :-

Happy designing, engineers!

BHE3233 BTS4433 – Week 4 – Combinational Logic

Welcome to Week 4 of BHE 3233 and BTE4433. This week marks an important step in your journey as electrical and electronic engineering students, as you begin connecting theoretical concepts with actual hardware implementation. You have now moved beyond just understanding logic on paper—you are starting to build and test real digital systems using Verilog and FPGA tools.

We began the week with a refresher on binary operations, which form the foundation of all digital systems. Understanding how numbers are represented and manipulated in binary is essential, as every digital circuit ultimately operates on combinations of 0s and 1s. From there, we transitioned into describing combinatorial logic using Verilog, focusing specifically on adders.

You were first introduced to the half adder, a simple circuit that takes two binary inputs and produces a sum and a carry output. Although basic, it is an important building block in digital design. We then extended this concept to the full adder, which includes a carry-in input, allowing multiple adders to be connected together. This idea of chaining adders is fundamental in designing circuits capable of handling multi-bit arithmetic operations.

To give you a broader perspective, we briefly explored more advanced adder designs such as the ripple carry adder and the carry look-ahead adder. The ripple carry adder is straightforward but can be slow because each carry must propagate through every stage. In contrast, the carry look-ahead adder improves speed by predicting carry signals in advance, although it comes with increased design complexity. These concepts will become more meaningful as you encounter larger and faster digital systems in the future.

 

 

 

Before moving into Lab 1, we started with Lab 0, which focused on simulation. In this lab, you worked with two files: number.v and number_tb.v. The goal was to simulate your design using ModelSim and observe how digital signals behave over time. This is a critical step in digital design, as simulation allows you to verify correctness before implementing your code on actual hardware.

In number.v, you were given a basic up-counter design capable of driving a 7-segment display on the FPGA board. Through this, you explored several important Verilog concepts, including top module declaration, the use of wire data types, and bit buses for representing multi-bit signals. You also examined conditional statements such as if-else, as well as basic mathematical operations within Verilog. By analyzing the waveform output in ModelSim, you were able to see how signals change over time and how your design behaves in response to different inputs. This helped build your understanding of timing and signal relationships in digital circuits.

During the Lab 1, which focused on implementing a running LED design on the DE10-Lite FPGA Board. The task required you to write Verilog code, compile it, assign the correct pins for the 10 LEDs on the board, and program the FPGA. The result was a sequence of LEDs lighting up from one end of the board to the other, demonstrating a simple but effective hardware implementation of your design.

This lab was significant because it introduced you to the complete FPGA workflow, from coding to physical output. Many of you experienced the process of compiling your design, resolving errors, performing pin assignments, and finally observing your design working on actual hardware. This transition from simulation to real-world implementation is a key milestone in your learning.

 

Thank you Lim for the video shot.

Some common challenges were observed during the session, particularly issues with the hardware not being recognized by your computer. In most cases, this was due to problems with the USB-Blaster driver installation. Ensuring that the driver is properly installed and that the device is correctly detected by the system is crucial. Checking the device manager, trying different USB ports, or reinstalling the driver can often resolve these issues.

 

Overall, this week has equipped you with essential skills in designing combinatorial circuits using Verilog and implementing them on an FPGA platform. You should now have a clearer understanding of how basic arithmetic circuits are built and how digital designs move from code to hardware.

As we move forward, make sure you are comfortable with both your Verilog coding and FPGA setup. The concepts and skills from this week will serve as the foundation for more advanced topics in the coming weeks. If you are still facing issues, especially with hardware setup, it is important to address them early.

See you in Week 5.

BHE3233 BTS4443 – Week 2 – Digital System Design – Introduction Hardware Description Language

Welcome to Week 2 of BHE 3233. This week, we began exploring one of the most important tools in digital design—Hardware Description Language (HDL). Unlike traditional programming languages, HDL is used to describe hardware behavior and structure, allowing us to design, simulate, and eventually implement digital systems on hardware such as FPGAs.

We focused on Verilog, one of the most widely used HDLs in industry. The goal this week was to familiarize you with the basic syntax and structure of Verilog code. You learned how a typical Verilog module is written, starting with the module declaration, defining inputs and outputs, and ending with the endmodule keyword. Understanding this structure is essential, as every design you create will follow this format.

We also explored key syntax elements in Verilog. This included the use of data types such as wire and reg, which are used to represent connections and stored values in a circuit. You were introduced to basic operators, including logical, relational, and arithmetic operators, which allow you to describe how signals interact. Additionally, we discussed procedural blocks such as always and initial, as well as conditional statements like if-else, which enable you to define how your circuit behaves under different conditions.

Another important concept covered this week was the idea of combinational versus sequential logic in Verilog. While we will go deeper into these topics later, it is important to recognize how Verilog can be used to represent both types of circuits through different coding styles.

A major highlight of the week was the introduction to the testbench. A testbench is a separate Verilog module used to simulate and verify your design. Instead of implementing your code directly on hardware, a testbench allows you to apply input stimuli and observe the output in a controlled environment. This helps you identify errors early and ensures that your design behaves as expected.

In your testbench files, you learned how to declare signals, instantiate your design module, and apply different input combinations over time. You also explored how simulation tools display outputs in the form of waveforms, which provide a visual representation of signal changes. This is a critical skill, as simulation and verification are essential steps in any digital design workflow.

Overall, Week 2 laid the foundation for everything that follows in this course. You now have a basic understanding of how to write Verilog code and how to test your designs using a testbench. These skills will be used extensively in the coming weeks as we move into more complex digital circuits and FPGA implementation.

As you continue practicing, focus on writing clean and correct syntax, and always verify your designs using a testbench before moving forward. This habit will save you a lot of time and help you become a more effective digital designer.

See you in next week!

Week 1 – BHE3233 BTS443 – Digital System Design – Introduction to FPGA Design

Welcome to Week 1 of BHE3233 Digital System Design and BTE4433 Electronic System Design!
Whether you are aiming to master the intricacies of digital logic or build complex electronic systems, this semester will take you on a journey from writing abstract code to deploying robust, optimized physical hardware.
To kick things off, let’s take a bird’s-eye view of the entire course roadmap (Modules 1, 2, and 3), and then dive into the core topics covered this week in Chapter 1: Introduction to IC Design and HDL Environment.
The Course Roadmap: What to Expect This Semester
Our curriculum is structured into three progressive modules that mirror the industry-standard FPGA design workflow:
      1. Module 1: Fundamentals of IC and HDL Design This module lays the groundwork.
        • You will explore the digital design abstraction hierarchy—from behavioral down to physical implementation levels.
        • You will be introduced to Hardware Description Languages (HDL), specifically Verilog, learning its syntax and various modeling styles (structural, dataflow, and behavioral).
        • Most importantly, you will learn how to verify your digital circuits before touching any hardware by constructing testbenches and performing functional simulations using ModelSim.
      2. Module 2: RTL Design and Synthesis Once you know how to write and simulate Verilog, Module 2 focuses on transformation.
        • You will learn how Register Transfer Level (RTL) designs are synthesized into actual hardware components.
        • We will explore technology mapping and gate-level netlist generation using Intel Quartus Prime tools, teaching you how to analyze compilation reports and evaluate resource utilization.
      3. Module 3: Timing Analysis and Design Optimization Synthesizing code into gates is only half the battle; the hardware must also run at the correct speed.
        • This final module emphasizes practical hardware deployment on the Altera DE10-Lite FPGA board.
        • You will dive into Static Timing Analysis (STA), learning about critical paths, setup and hold times, and slack.
        • You will also apply optimization techniques like pipelining to hit timing closure before presenting your final capstone project.

Week 1 Deep Dive: Chapter 1 Overview

This week, we begin with Chapter 1: Introduction to IC Design and HDL Environment, which sets the stage for everything you will build.
    1. The Evolution of Logic Devices
      • Before modern FPGAs (Field-Programmable Gate Arrays) dominated the market, engineers relied on older programmable logic devices.
      • We start by gaining a historical perspective on the evolution from early PLAs (Programmable Logic Arrays), PALs (Programmable Array Logic), and PLDs (Programmable Logic Devices) to the highly advanced FPGA systems we use today.   
    2. FPGAs vs. Microcontrollers vs. ASICs
      • Why use an FPGA? We compare FPGAs against standard Microcontrollers (MCUs) and Application-Specific Integrated Circuits (ASICs).
        1. Microcontrollers execute instructions sequentially and have fixed architectures, making them great for embedded control but slower for massive computations.
        2. ASICs are highly optimized for specific tasks and boast high performance, but they are expensive to develop and their hardware cannot be changed once fabricated.
        3. FPGAs offer the best of both worlds: they provide high parallel processing power and are highly reconfigurable, meaning you can reprogram their internal logic to suit different designs at a moderate cost.

 

3. Design Abstraction Levels

Modern digital design is too complex to build gate-by-gate. Instead, we use different abstraction levels to manage complexity:

      • Behavioral Modeling

Describes the algorithm or behavior using high-level programming constructs (like if-else and case statements).

      • Dataflow Modeling

Describes how data moves through the circuit using Boolean expressions and continuous assignments.

      • Structural Modeling (Gate-Level)

Explicitly describes how individual components and logic gates are wired together physically.

4. The FPGA Design Flow

Bringing a digital concept to life requires a strict engineering workflow. This week, we cover the general steps you will repeat throughout the semester:

      1. Design Entry
        • Writing your Verilog HDL code to describe the circuit.
      2. Synthesis
        • The Quartus software translates your high-level HDL into a gate-level netlist, optimizing the logic and mapping it to the FPGA’s specific resources (like Look-Up Tables and Flip-Flops).
      3. Implementation
        • The software physically places the logic blocks on the FPGA chip and routes the microscopic wires between them.
      4. Timing Analysis
        • Checking to ensure the physical routing delays don’t violate strict timing rules (setup and hold times).
      5. Bitstream Generation
        • Generating a .sof binary configuration file that gets downloaded to the FPGA to physically program it.

5. Our Hardware and Software Environment

To accomplish all of this, we will be getting hands-on with industry-standard tools:

      1. The Hardware
        • The DE10-Lite Development Board, powered by an Intel MAX 10 FPGA. It comes packed with switches, LEDs, 7-segment displays, and plenty of I/O for our projects.
      2. The Software
        • You will learn to navigate Intel Quartus Prime Lite Edition for compiling and synthesizing your code, alongside ModelSim for running your vital pre-hardware functional simulations.

 

Take time this week to install Quartus Prime and ModelSim, familiarize yourself with the software interfaces, and review the DE10-Lite board documentation.Next week, we will start writing real Verilog HDL code and designing our first digital circuits!

Learning from Practice – Reflections on a Sharing Session with Prof Hilman

I recently attended a sharing session by Prof Hilman on research and teaching technology in Electronic Engineering, and it left a strong impression, particularly in terms of how much care and thought he puts into his teaching.

What stood out most was Prof Hilman’s creativity and long-term commitment to his classroom. Over the years, he has developed a series of learning kits that are used across different levels of the programme, from first year right up to final year. These kits are not one-size-fits-all; instead, they are modular, covering topics ranging from analog electronics and RF to sensor design. You can clearly see that they were built with progression in mind, allowing students to grow into the complexity of the subject rather than being overwhelmed by it.

Having developed teaching kits myself, mainly for mini robotics, embedded systems, and IoT, I found myself very much on the same page. Designing kits for teaching is rewarding, but it also comes with its own set of challenges, especially when it comes to deciding how much to give students and how much to leave for them to figure out on their own.

When I talk about “giving everything,” I’m referring to situations where kits / modules that are highly prepared: dedicated PCBs, predefined functional blocks, and ready-to-use modules. This certainly helps students get started more quickly and reduces frustration. At the same time, we sometimes forget that designing those things, like laying out a PCB or deciding how a circuit or functions (in software programming) should be structured, is also an important part of learning.

On the other end of the spectrum is giving students only the bare minimum and expecting them to build everything from scratch. While this can be very powerful for learning, it is not always easy to manage in a real classroom. Students learn at different speeds, and ensuring that everyone can keep up within a fixed semester timeline can be quite challenging.

This is something I’ve often thought about through the lens of the white‑box versus black‑box approach, which I also discussed in my earlier works on tiered scaffolding approaches in Python Slider Game and the STEMCube platform. Both approaches have their place, and the real question is how to strike the right balance.

During the session, I raised this question with Prof Hilman, and we had a good discussion around it. What I found particularly insightful was his view that modularity helps bridge the gap between these two extremes. By designing kits in modules, we can decide which parts are “given” and which parts students are encouraged to develop themselves. As students progress, more of the system can be opened up to them. This makes the learning process more flexible and helps accommodate different learning paces within the same class.

We also touched briefly on the role of AI in analog design, especially during the early design and optimisation stages. While still an evolving area, it sparked an interesting discussion about how such tools might eventually support both teaching and research in electronics engineering.

Overall, the session was a good reminder that effective teaching innovation doesn’t come from choosing one extreme over another, but from carefully designing learning experiences that evolve with students. Prof Hilman’s modular approach is a practical example of how this balance can be achieved, and it’s certainly something I will continue to reflect on in my own teaching practice.

Nurul – March 9th

BHE3233 – Week 12 – Project Development

It’s project time =)

This semester in BHE3233 – Digital System Design, we’re exploring practical world of digital hardware by implementing real-time, embedded digital systems using the DE10-Lite FPGA board. Building on the fundamentals of Verilog, FSMs, and RTL design we’ve covered, students now have the opportunity to apply their knowledge through these exciting hands-on projects. Each project emphasizes different aspects of digital design—from FSM sequencing to pipelining and datapath architecture.

These projects were carefully curated to cover a wide range of course outcomes, from combinational and sequential logic design to system-level implementation using FSMs and RTL pipelines. Students not only reinforce theoretical understanding but also gain confidence in developing real-time FPGA applications using Verilog on the DE10-Lite board.

Before jumping into their projects, the students have already completed structured labs covering:-

        • FSM design and simulation

        • RTL pipelining

        • Clocking and timing constraints

        • Static timing analysis

        • 7-segment display interfacing

        • Debouncing and switch inputs

These foundational skills are directly applicable to the project implementations.

Here’s a detailed look at the 6 project titles offered this semester:-

1. Morse Code Encoder and LED Blinker

Objective – Design a finite state machine (FSM)-based system that converts input characters (A-Z, 0-9) into Morse code and blinks an LED accordingly.

Key Features –

      • Input a hardcoded message (or via DIP switches)

      • FSM handles character-to-Morse conversion (dot and dash)

      • LED blinks in Morse timing format

      • Optional – Display current character on a 7-segment display during encoding

Learning Outcomes – FSM design, output timing control, sequential logic, user interaction.

2. Basic 8-bit RISC CPU Implementation

Objective – Build a basic 8-bit CPU that supports core instructions such as ADD, SUB, LOAD, STORE, and JMP.

Key Features –

  • 4 to 8 general-purpose registers

  • Instruction decoder and ALU unit

  • ROM-based instruction memory and RAM-based data storage

  • Output status or values via LEDs or 7-segment display

Learning Outcomes – Datapath design, FSM for control unit, memory interfacing, and simple instruction architecture.

3. Parallel Multiplier Using RTL Pipelining

Objective – Design a high-speed 8-bit parallel multiplier using RTL pipelining techniques.

Key Features –

  • Inputs via DIP switches or pushbuttons

  • Multi-stage pipelining of partial products

  • Output result on 7-segment displays

  • Compare pipelined design with pure combinational multiplier in terms of:-

      1. Critical path delay

      2. Maximum clock frequency

      3. FPGA logic utilization

      4. Throughput

Learning Outcomes – Pipelined architecture, latency vs. throughput, performance analysis.

4. Digital Stopwatch with Lap Function

Objective – Create a stopwatch with basic timing functions and lap time capture.

Key Features:

      1. Start/Stop/Reset controls via pushbuttons

      2. FSM-based timing logic

      3. 4-digit multiplexed 7-segment display

      4. Capture and display lap time on button press

Learning Outcomes – Sequential system design, timing counters, 7-segment multiplexing, user interface design.

5. Password-Protected Digital Lock

Objective – Develop a digital locking system with password protection using FSM.

Key Features –

  • User password entry via DIP switches

  • Status feedback through LEDs or 7-segment

  • Lock/unlock logic with real-time comparison

  • Optional: Add retry limit and lockout on failed attempts

Learning Outcomes – FSM logic, comparison algorithms using shift registers, and embedded security logic.

6. Dice Game Controller

Objective – Simulate a simple 2-player dice game with visual feedback and turn-based logic.

Key Features –

  • Pushbutton to initiate dice roll

  • Use LFSR (Linear Feedback Shift Register) to generate pseudo-random numbers (1–6)

  • Output displayed using 7-segment or LED

  • FSM handles player turns and win conditions

Learning Outcomes – Random number generation using LFSR, FSM game logic, 7-segment display control.

 

Today, each group presented their project progress. Well done!

  • Functional demo on the DE10-Lite board

  • Timing and performance analysis

  • Challenges and solutions in design

Looking forward to final outcome and submission in Kalam!