The book is finally in =).
There is a specific kind of satisfaction in hardware engineering—the moment a conceptual logic circuit transitions from a schematic to a functional physical implementation. My fascination with this process began in 1999 during my undergraduate studies under Professor Othman Sidek. Back then, the ability of an FPGA to house a vast array of logic functions felt revolutionary.
It all started with a project in my Digital Electronics 2 subject. I remember it vividly, we built an automated counter for badminton matches. The digital logic system was designed to detect whether a shuttlecock landed in or out of bounds to assist the umpire in ruling points. That small-scale project served as the gateway to a much deeper exploration into digital systems.
From Undergraduate Roots to GSM Architecture
By the time I reached my final year project, I was diving deep into digital systems for GSM communication modules. Through a family connection—my cousin, who was then a technician for a leading telecommunications provider—I gained invaluable access to the industry standards of the time.
I was particularly focused on implementing Convolutional Encoders, which were essential for error correction in mobile networks. At the time, we worked across the five primary channel types:
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TCH/FS (Full Rate Speech)
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TCH/HS (Half Rate Speech)
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FACCH (Fast Associated Control Channel)
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SACCH (Slow Associated Control Channel)
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SDCCH (Standalone Dedicated Control Channel)
The successful implementation of these designs wasn’t just a hurdle to pass for graduation, it was the foundation of my continued passion with digital logic =p
Fast forward to 2021, I returned to the classroom to teach Digital System Design. Re-engaging with the subject after years in the field felt like a homecoming. During this period, I began supervising Phuah Soon Eu on the project involving the implementation of metaheuristic algorithms on IC chips.
The inherent challenges of translating high-level algorithms into hardware were tackled: managing floating-point arithmetic, optimizing RAM architectures, and modifying algorithmic flows to suit the rigid requirements of digital implementation.
Introducing the Book: A Practical Path for the Novice
Through the project implementation, a persistent “missing link” in technical FPGA education literature. There is a steep cliff between learning basic Verilog and understanding the professional constraints of a production-ready FPGA design.
To bridge this gap, this book is introduced.
Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis
The philosophy is simple: The best way to learn a system is to build it. We designed this text to guide the reader through three critical phases:
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Foundations: Introduction to FPGA architecture and Hardware Description Language (HDL).
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Synthesis: A deep dive into RTL modeling and the complexities of Static Timing Analysis (STA).
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Implementation: Mastering FPGA-specific design and the art of optimization.
Moving from Functional to Professional
This book is specifically written for those at the “Novice to Early-Intermediate” stage. It is for the designer to learn to perform a functional simulation but needs to learn how to read synthesis reports, meet specific timing targets, and redesign circuits with objective-driven outcomes.
It has been a privilege to author this with Phuah Soon Eu, and we hope this work serves as a catalyst for the next generation of digital designers—much like a badminton counter did for me decades ago :).
