BHE3233 BTS4433 – Week 7 – Sequential RTL – Lab 4

Welcome to Week 7! This week, we took a massive leap in our digital design journey by exploring Register Transfer Level (RTL) sequential circuits. Unlike combinational circuits, sequential circuits have memory, meaning their outputs depend not only on current inputs but also on previous input
history. At the heart of these sequential designs is the Finite State Machine (FSM).
In digital design, FSMs are used to control system behavior by transitioning between a finite number of states based on inputs and clock cycles.
When we build FSMs in Verilog, we generally divide the architecture into three main blocks:
        1. The State Register: This is a synchronous block (using always @(posedge clk)) that updates the current state to the next state at every clock edge, or resets it when a reset signal is triggered.
        2. The Next-State Logic: A combinational block that evaluates the current state and external inputs to determine what the next state should be.
        3. The Output Logic: A combinational block that generates the output signals based on the current state (Moore machine) or both the current state and inputs (Mealy machine).
In class, we looked at a practical example: a sequence detector acting as a lock that opens whenever the serial bit pattern “1011” is achieved.
Before writing any Verilog code, it is incredibly important to derive your state machine on pen and paper first. Drawing an abstract state diagram ensures your states and transition logic actually make sense.
For the “1011” detector, our state diagram tracks how much of the pattern we have seen so far:
        1. S0: Nothing matched yet.
        2. S1: Matched “1”.
        3. S2: Matched “10”
        4. S3: Matched “101”
        5. S4: Matched the full “1011” sequence (this is where the output goes high).
By mapping out the transition arrows—such as moving from S1 to S2 if the input is 0, or dropping back to S0 if the sequence is broken—you establish the exact mathematical behavior your next-state logic block needs to model.
Hands-On: Lab 4 and the Satellite Communication System
Once we nailed down the state diagrams on paper, we moved into the hardware phase with Lab 4: Finite State Machine for Satellite Communication Link
In real picosatellite systems, communication links require a strict, multi-stage initialization and termination process . You simulated this exact scenario using a four-state FSM:
      1. IDLE: Waiting for the start command.
      2. LINK_ESTABLISH: Attempting the communication handshake.
      3. DATA_TRANSFER: The active data transmission session
      4. LINK_TERMINATE: Securely closing the session 
During the lab, you mapped your DE10-Lite board’s switches to act as the transition triggers (e.g., SW0 to start communication, SW1 to signify link established) and used the LEDs to track which state the FSM was currently in.
By verifying the state transitions in a ModelSim simulation and testing it directly on the physical board, you successfully built a control system identical to those used in real-time embedded space missions !
Keep practicing drawing those state diagrams on paper before jumping into Quartus. See you next week!

 

2026 Book :) Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis

The book is finally in =).

There is a specific kind of satisfaction in hardware engineering—the moment a conceptual logic circuit transitions from a schematic to a functional physical implementation. My fascination with this process began in 1999 during my undergraduate studies under Professor Othman Sidek. Back then, the ability of an FPGA to house a vast array of logic functions felt revolutionary.

It all started with a project in my Digital Electronics 2 subject. I remember it vividly, we built an automated counter for badminton matches. The digital logic system was designed to detect whether a shuttlecock landed in or out of bounds to assist the umpire in ruling points. That small-scale project served as the gateway to a much deeper exploration into digital systems.

From Undergraduate Roots to GSM Architecture

By the time I reached my final year project, I was diving deep into digital systems for GSM communication modules. Through a family connection—my cousin, who was then a technician for a leading telecommunications provider—I gained invaluable access to the industry standards of the time.

I was particularly focused on implementing Convolutional Encoders, which were essential for error correction in mobile networks. At the time, we worked across the five primary channel types:

      1. TCH/FS (Full Rate Speech)

      2. TCH/HS (Half Rate Speech)

      3. FACCH (Fast Associated Control Channel)

      4. SACCH (Slow Associated Control Channel)

      5. SDCCH (Standalone Dedicated Control Channel)

The successful implementation of these designs wasn’t just a hurdle to pass for graduation, it was the foundation of my continued passion with digital logic =p

Fast forward to 2021, I returned to the classroom to teach Digital System Design. Re-engaging with the subject after years in the field felt like a homecoming. During this period, I began supervising Phuah Soon Eu on the project involving the implementation of metaheuristic algorithms on IC chips.

The inherent challenges of translating high-level algorithms into hardware were tackled: managing floating-point arithmetic, optimizing RAM architectures, and modifying algorithmic flows to suit the rigid requirements of digital implementation.

Introducing the Book: A Practical Path for the Novice

Through the project implementation, a persistent “missing link” in technical FPGA education literature. There is a steep cliff between learning basic Verilog and understanding the professional constraints of a production-ready FPGA design.

To bridge this gap, this book is introduced.

Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis

The philosophy is simple: The best way to learn a system is to build it. We designed this text to guide the reader through three critical phases:

      1. Foundations: Introduction to FPGA architecture and Hardware Description Language (HDL).

      2. Synthesis: A deep dive into RTL modeling and the complexities of Static Timing Analysis (STA).

      3. Implementation: Mastering FPGA-specific design and the art of optimization.

Moving from Functional to Professional

This book is specifically written for those at the “Novice to Early-Intermediate” stage. It is for the designer to learn to perform a functional simulation but needs to learn how to read synthesis reports, meet specific timing targets, and redesign circuits with objective-driven outcomes.

It has been a privilege to author this with Phuah Soon Eu, and we hope this work serves as a catalyst for the next generation of digital designers—much like a badminton counter did for me decades ago :).

Raspberry Pi Programming 2026/1 – KV Tawau

*UMPSA STEM Lab Raspberry Pi Programming Synopsis can be found here.

In the Raspberry Pi IoT session, 20 students and teachers from Kolej Vokasional Kulim were introduced to the concept of the Internet of Things (IoT) using Raspberry Pi on the UMP STEM Cube, a pico-satellite learning kit specifically designed to facilitate engineering learning.

The content covered basic digital input/output operations on onboard LEDs, as well as topics such as dashboard design using gyro meter and BMU280 sensor data, including collecting and storing data in a cloud database. Participants learned to interface sensors with Raspberry Pi boards and develop IoT applications for real-world scenarios. The session provided students with valuable insights into IoT technology and its applications in various domains.

A special appreciation is extended to Cikgu Shufi from KV Tawau, Sabah for coordination in facilitating communication between the participants and the UMPSA STEM Lab :).

Nurul April 26th

 

Raspberry Pi Programming 2026/2 – KV Kulim

*UMPSA STEM Lab Raspberry Pi Programming Synopsis can be found here.

In the Raspberry Pi IoT session, 28 students and teachers from Kolej Vokasional Kulim were introduced to the concept of the Internet of Things (IoT) using Raspberry Pi on the UMP STEM Cube, a pico-satellite learning kit specifically designed to facilitate engineering learning.

The content covered basic digital input/output operations on onboard LEDs, as well as topics such as dashboard design using gyro meter and BMU280 sensor data, including collecting and storing data in a cloud database. Participants learned to interface sensors with Raspberry Pi boards and develop IoT applications for real-world scenarios. The session provided students with valuable insights into IoT technology and its applications in various domains.

A special appreciation is extended to Cikgu Aminah dan Cikgu Huraiah from KV Kulim for coordination in facilitating communication between the participants and the UMPSA STEM Lab :).

Nurul April 26th

 

 

 

Raspberry Pi Programming 2026/1 – Mentor Training

*UMPSA STEM Lab Raspberry Pi Programming Synopsis can be found here.

In the Raspberry Pi IoT session, 24 UMPSA mentors were introduced to the concept of the Internet of Things (IoT) using Raspberry Pi on the UMP STEM Cube, a pico-satellite learning kit specifically designed to facilitate engineering learning.

The content covered basic digital input/output operations on onboard LEDs, as well as topics such as dashboard design using gyro meter and BMU280 sensor data, including collecting and storing data in a cloud database. Participants learned to interface sensors with Raspberry Pi boards and develop IoT applications for real-world scenarios. The session provided students with valuable insights into IoT technology and its applications in various domains.

A special appreciation is extended to En Mohd Jamil Jaafar for coordination in facilitating communication between the participants and the UMPSA STEM Lab :).

 

IMG_4939

TTT – Arduino and Edge Computing

As part of ongoing efforts to strengthen digital pedagogy and future-ready STEM education, a Train-the-Trainer (TTT) Teachers Training Programme was successfully conducted for teachers from across Pahang, focusing on Arduino programming using ESP platforms and Edge Impulse for image classification.

The programme was designed to equip teachers with hands-on experience in digital making while introducing fundamental concepts of machine learning, particularly in the context of computer vision and image classification.

Programme Objectives

The main objectives of this TTT programme were to:

    1. Familiarise teachers with digital making concepts using Arduino and ESP-based microcontrollers
    2. Provide foundational understanding of machine learning, specifically image classification
    3. Introduce Edge Impulse as an accessible platform for developing embedded AI applications
    4. Enable teachers to confidently integrate AI, IoT and embedded systems into classroom teaching and student projects
    5. Support the development of future-ready educators aligned with Industry 4.0 and AI-driven education

Hands-On Learning with Arduino and ESP

During the training, teachers were introduced to Arduino programming on ESP platforms (such as ESP32), covering:

    1. Basic Arduino IDE setup and programming workflow
    2. Interfacing ESP boards with peripherals (camera modules, sensors)
    3. Understanding microcontroller capabilities for edge computing
    4. Deploying lightweight AI models on embedded devices

This hands-on approach allowed participants to move beyond theory and experience how hardware, software and AI intersect in real-world applications.

Introduction to Edge Impulse and Image Classification

A key highlight of the programme was the introduction to Edge Impulse, a powerful yet beginner-friendly platform for embedded machine learning.

Teachers learned:

    1. The fundamentals of machine learning and image classification
    2. How to collect image datasets using ESP camera modules
    3. Data labelling and training simple image classification models
    4. Deploying trained models directly onto ESP devices for on-device inference (edge AI)

Through guided activities, participants successfully implemented basic image classification tasks, gaining confidence in applying AI concepts without requiring advanced programming or mathematical backgrounds.

Building Confidence in Teaching AI and Digital Making

Beyond technical skills, the programme emphasised pedagogical readiness. Discussions and activities focused on:

    1. Translating complex AI concepts into classroom-friendly learning activities
    2. Designing project-based learning (PBL) tasks using Arduino and AI
    3. Encouraging student creativity, problem-solving and ethical awareness in AI use
    4. Aligning AI and digital making activities with school STEM curricula

Teachers shared ideas on how these technologies could be adapted for subjects such as Asas Sains Komputer, Reka Bentuk Teknologi, STEM projects and robotics clubs.

Impact and Way Forward

This TTT programme marked an important step in empowering educators in Pahang with practical skills in embedded systems, AI and digital innovation. By strengthening teachers’ confidence and competency, the programme supports the broader goal of cultivating AI-literate students who are prepared for future technological challenges.

Moving forward, participants are expected to:

    1. Implement Arduino- and AI-based projects in their schools
    2. Act as multipliers, training fellow teachers and students
    3. Contribute to a growing ecosystem of responsible, ethical and sustainable AI education

Conclusion

The Arduino–ESP–Edge Impulse TTT programme demonstrates that machine learning and AI are no longer confined to advanced laboratories. With the right tools and training, educators can bring AI-powered digital making into everyday classrooms—sparking curiosity, innovation and future-ready skills among students.

This initiative reinforces the commitment to strengthening STEM and AI education at the grassroots level, ensuring teachers remain at the heart of Malaysia’s digital and educational transformation.

BHE3233 BTS4433 – Week 6 – FPGA Implementation of Combinational RTL – Lab 3

This week, we continued our exploration of combinatorial circuits, focusing on Lab 3 (Session 5): Implementation and Comparison of Ripple Carry Adder (RCA) and Carry Look-Ahead Adder (CLA). This lab builds on students’ foundational understanding of digital logic and provides hands-on experience with adder architectures that are central to arithmetic logic units (ALUs).

Lab Objectives

The key objectives of this lab were to:

      1. Design and implement 4-bit Ripple Carry Adders (RCA) and 4-bit Carry Look-Ahead Adders (CLA)
      2. Perform functional verification using selected test vectors
      3. Implement both designs on an FPGA platform
      4. Analyze and compare post-implementation parameters using Quartus post-implementation reports
      5. Introduce basic ALU functionality, focusing on multiplexing using case statements and transitioning toward decoder-based designs

Adder Design and Implementation

Students designed both adders using structural and behavioral modeling approaches in HDL:

  • Ripple Carry Adder (RCA):
    A straightforward adder where each full adder waits for the carry from the previous stage. This simplicity comes at the cost of increased propagation delay.
  • Carry Look-Ahead Adder (CLA):
    A faster alternative that computes carry signals in parallel using generate and propagate logic, significantly reducing carry propagation delay.

Both designs were synthesized and deployed on the FPGA to observe real hardware performance, not just simulation results.

Functional Testing

During functional testing, several input combinations were validated to ensure correctness:

      • A = 5 (0101), B = 3 (0011)
        • Result: 8 (1000)
        • Verified correct operation for both RCA and CLA.

      • A = 15 (1111), B = 1 (0001)
        • Result: 0 with carry-out = 1
        • This test demonstrated carry spill-over, confirming correct handling of overflow conditions.

These cases helped reinforce how carry propagation affects outputs and highlighted the functional equivalence of RCA and CLA despite architectural differences.

 

Post-Implementation Analysis (Quartus)

An important part of this lab was analyzing the post-implementation reports in Quartus.

 

Students were tasked with extracting and comparing the following parameters for both adder implementations:

        • Logic Elements (LEs) Used
          How much FPGA hardware is consumed by RCA versus CLA.
        • Combinational Functions
          Insight into the complexity of logic synthesized by the toolchain.
        • Maximum Clock Frequency (Fmax)
          The highest achievable clock rate based on timing constraints.
        • Critical Path Delay
          The longest combinational delay path, which is especially important when comparing RCA and CLA performance.

As expected, the RCA generally exhibited a longer critical path delay due to serial carry propagation, while the CLA achieved a higher maximum clock frequency, demonstrating its advantage in speed-critical designs.

In digital circuits, Fmax (maximum clock frequency) tells us how fast a circuit can run when a clock is used. It depends on the critical path, which is the longest delay through the combinational logic. Signals must be able to travel along this path and settle before the next clock edge arrives. If the critical path is long, the circuit needs a slower clock. In this lab, the RCA has a longer critical path because the carry must pass through each bit one by one, while the CLA reduces delay by calculating carries in parallel.

When checking the Quartus Timing Analysis Report, students noticed that it shows “No Fmax” and “No clock properties to report.” This is normal for this lab. Both the RCA and CLA designs are purely combinational and do not include any clocked elements such as flip-flops or registers. Since there is no clock defined in the design, Quartus cannot calculate Fmax. Fmax is only reported for sequential circuits where data moves from one register to another using a clock. For this reason, Quartus only reports logic usage and combinational delay. Once registers are added in future labs—such as in a registered ALU or datapath—Fmax and full timing information will become available.

To clearly observe the difference in hardware utilization, the total number of logic gates and Configurable Logic Elements (CLEs) used in the system can be analyzed by implementing both a 32-bit Carry Look-Ahead Adder (CLA) and a 32-bit Ripple Carry Adder (RCA). By experimenting with these two adders under identical design conditions, a direct comparison can be made. This allows the differences in resource usage to be clearly identified, where the CLA generally requires more gates and CLEs due to its complex carry logic, while the RCA uses fewer resources but operates with a longer propagation delay.

The example design above employs a genvar as a compile-time counter within a Verilog generate loop to create the 32 stages of the ripple carry adder. The counter variable i controls the instantiation of each full adder, where A[i] and B[i] represent the operand bits at position i, and carry[i] and carry[i+1] form the carry chain between adjacent stages. This approach improves scalability and code modularity, allowing the adder width to be easily adjusted without altering the underlying architecture. Importantly, the use of a counter does not affect the synthesized hardware, as the loop is unrolled during synthesis.

Introduction to Basic ALU Concepts

In the latter part of the lab, we began transitioning from simple adders to basic ALU design concepts:

      1. Students implemented a simple ALU capable of performing multiple operations.
      2. A case statement was used to implement a multiplexer that selects the desired operation based on an opcode.
      3. This approach helped students understand how operation selection works internally within an ALU.

We also discussed the next step in this progression: moving from case-based multiplexing toward decoder-based control logic, which scales better for more complex ALU designs.

You can also take this up a level by having your ALU with output assigned to 7 segment display:-

 

Key Takeaways

By the end of this lab, you should be able to:

      1. Understand the architectural and performance differences between RCA and CLA
      2. Validate combinational circuits through simulation and FPGA implementation
      3. Interpret FPGA post-implementation reports to justify design trade-offs
      4. See how simple adders evolve into more complex building blocks, such as ALUs

This lab serves as a crucial bridge between basic combinational logic and more advanced processor datapath components, setting the stage for upcoming topics in sequential logic and CPU design.

BHE3233 BTS4433 – Week 5 – FPGA Implementation of Combinational RTL

This week is important as we move from theoretical concepts to hands-on hardware implementation. You will be tackling Pre-Labs (Sessions 1 & 2) and Labs 1 & 2 (Sessions 3 & 4).

To succeed in this course and meet our core learning outcomes—specifically CO3, which focuses on developing FPGA designs using industry best practices—you must follow a structured approach.

Phase 1: The Foundation (Pre-Lab Sessions 1 & 2)

Before touching the hardware, you must set up your digital environment. These sessions focus on Project Setup and Functional Verification.

      • Software Installation: Ensure you have Intel Quartus Prime Lite Edition (Version 18.1) and ModelSim installed on your computer.

      • Project Creation: Launch the New Project Wizard in Quartus. Critical step: You must target the specific FPGA device on our board: MAX 10 – 10M50DAF484C7G.

  

      • Functional Simulation: Use ModelSim to verify your logic before synthesis. This allows you to catch bugs in a software environment where signals are easy to trace.

Phase 2: Hands-On Implementation (Labs 1 & 2)

Now, it’s time to bring your code to life on the DE10-Lite FPGA Board.

Lab 1: Blinking LEDs (Session 3)

In this lab, you will learn to control the board’s ten user-defined LEDs.

      • The Logic: You will write a Verilog module utilizing a counter to create a delay.

      • Key Tip: Remember that the onboard clock runs at 50 MHz. Your counter must be large enough (at least 25 bits) to create a blink visible to the human eye.

Lab 2: Switch Inputs and Debouncing (Session 4)

Mechanical switches are “noisy.” When you flip a switch, the signal “bounces” rapidly between high and low before settling.

  • The Challenge: You will implement Debounce Logic using a counter to ensure the FPGA only registers a clean, stable signal.

  • The Goal: Observe the difference between a direct switch-to-LED connection and one filtered through your debounce logic.

    How to Complete Your Lab Answer Sheets

Your lab worksheet is your evidence of learning. To receive full marks and satisfy CO3 requirements, every session entry must include:

  1. Unique Module Naming: To ensure individual work, you must prefix your top-level modules with your unique initials (e.g., AZ_LED_Blinking). Generic names will result in mark deductions.

  2. Verilog Code Snippets: Paste snapshots of your design module and your testbench.

  3. Simulation Waveforms: Provide ModelSim screenshots. Don’t just paste the image; add notes explaining the logic proof and calculating the clock cycles or frequency observed.

  4. Implementation Reports: After compiling in Quartus, open the Compilation Report. You must include snapshots showing Resource Utilization (how many LUTs and Registers your design used).

    Final Submission Reminder

Once you have completed all activities and filled out your worksheet for Sessions 1 through 4:

  1. Verify that all dates are recorded correctly.

  2. Ensure every module name is unique to you / your team member.

  3. Upload the completed document to KALAM (after Lab 6 – Session 8).

Success in digital design comes from attention to detail. Double-check your pin assignments in the Pin Planner before programming, and always verify your timing slack in the Summary Report.

For those who are interested to explore more about Pin Planner, do explore this YouTube :-

Happy designing, engineers!

Publication 2026/3 – Empowering STEM Outreach Programs Through Collaborative Innovation

This year marks a meaningful milestone for the UMPSA STEM Lab — ten years of exploring how we can make STEM learning more engaging, accessible, and relevant. What started as a small initiative has gradually grown into a vibrant community of student mentors, university advisors, collaborators, teachers, and learners who share a common goal: nurturing curiosity and building meaningful digital making skills.

Thank you to all the student mentors, university advisors, and collaborators who have contributed to this journey. The STEM Lab is a collective effort of dedication, creativity, and willingness to experiment, refining teaching modules, and continuously improving the way STEM activities are delivered.

Over the past decade, the STEM Lab has served not only as an outreach platform but also as a space for pedagogical exploration. One of the central questions guiding our work has always been: What is the best way to introduce digital making and engineering thinking to learners? Through workshops, classroom activities, and collaborative programs, we have explored various approaches to make STEM learning more experiential and meaningful.

The programs focuses on developing effective teaching approaches for digital making skill sets and engineering concepts for school children and university students. Engineering concepts such as microcontrollers, IoT systems, FPGA-based digital design, and AI can often feel abstract when taught purely through lectures. The STEM Lab therefore serves as a platform to explore how these concepts can be delivered through hands-on, project-based learning, allowing students to connect theoretical knowledge with practical system development. In this sense, the lab functions as a living environment for engineering education, where ideas about teaching and learning can be tested and refined.

A major component of our work revolves around physical computing. Learning becomes far more engaging when students can interact with the physical world. Over the years, our modules have incorporated a wide range of microcontrollers (Arduino, ESPs), Raspberry Pi single-board computers, and embedded platforms, allowing learners to build systems that sense, respond, and interact with their environment. Through projects involving sensors, actuators, and robotics, students experience firsthand how software and hardware come together to create interactive systems.

Alongside hardware development, programming has always been a central pillar of the lab’s activities. To support learners with different levels of experience, we adopt a gradual progression from block-based programming to line-based programming. Beginners can quickly explore ideas through visual programming environments, while more advanced learners transition toward structured coding, developing deeper understanding of programming logic and computational thinking.

In recent years, the lab has also expanded into AI and embedded intelligence. Using platforms such as Edge Impulse, learners can experiment with edge AI applications such as image classification, demonstrating how machine learning models can run directly on embedded devices. These activities introduce students to the growing field of intelligent systems, where sensing, data processing, and decision-making can occur at the edge.

More recently, the STEM Lab has begun integrating FPGA-based modules into its learning ecosystem. By exposing learners to hardware-level digital design and parallel processing concepts, these modules provide a deeper understanding of how modern embedded systems are built. Together, these platforms form a learning progression, from physical computing to embedded systems, edge AI, and advanced digital architectures.

Looking back over the past ten years, the most meaningful outcome is not simply the number of workshops conducted or technologies introduced. Rather, it is the community that has grown around the STEM Lab. Many of our former mentors have continued their journeys in engineering, research, and education, carrying forward the spirit of exploration that began in the lab.

As we move into the next decade, we hope to continue expanding this ecosystem, strengthening collaborations with educators, researchers, and industry partners while refining how digital making and embedded systems are taught. The future of technology will require not only technical expertise but also creativity, curiosity, and collaboration. These are the values that the STEM Lab strives to cultivate.

To everyone who has been part of this journey — mentors, advisors, collaborators, teachers, and learners — thank you for contributing your time, ideas, and passion. The past ten years have been an incredible learning experience, and the next chapter promises to be just as exciting.