Category: Information

BHE3233 BTS4443 – Week 2 – Digital System Design – Introduction Hardware Description Language

Welcome to Week 2 of BHE 3233. This week, we began exploring one of the most important tools in digital design—Hardware Description Language (HDL). Unlike traditional programming languages, HDL is used to describe hardware behavior and structure, allowing us to design, simulate, and eventually implement digital systems on hardware such as FPGAs.

We focused on Verilog, one of the most widely used HDLs in industry. The goal this week was to familiarize you with the basic syntax and structure of Verilog code. You learned how a typical Verilog module is written, starting with the module declaration, defining inputs and outputs, and ending with the endmodule keyword. Understanding this structure is essential, as every design you create will follow this format.

We also explored key syntax elements in Verilog. This included the use of data types such as wire and reg, which are used to represent connections and stored values in a circuit. You were introduced to basic operators, including logical, relational, and arithmetic operators, which allow you to describe how signals interact. Additionally, we discussed procedural blocks such as always and initial, as well as conditional statements like if-else, which enable you to define how your circuit behaves under different conditions.

Another important concept covered this week was the idea of combinational versus sequential logic in Verilog. While we will go deeper into these topics later, it is important to recognize how Verilog can be used to represent both types of circuits through different coding styles.

A major highlight of the week was the introduction to the testbench. A testbench is a separate Verilog module used to simulate and verify your design. Instead of implementing your code directly on hardware, a testbench allows you to apply input stimuli and observe the output in a controlled environment. This helps you identify errors early and ensures that your design behaves as expected.

In your testbench files, you learned how to declare signals, instantiate your design module, and apply different input combinations over time. You also explored how simulation tools display outputs in the form of waveforms, which provide a visual representation of signal changes. This is a critical skill, as simulation and verification are essential steps in any digital design workflow.

Overall, Week 2 laid the foundation for everything that follows in this course. You now have a basic understanding of how to write Verilog code and how to test your designs using a testbench. These skills will be used extensively in the coming weeks as we move into more complex digital circuits and FPGA implementation.

As you continue practicing, focus on writing clean and correct syntax, and always verify your designs using a testbench before moving forward. This habit will save you a lot of time and help you become a more effective digital designer.

See you in next week!

Roundtable Discussion on Global Partnership – PIE WiSE and Project DiME

Universiti Malaysia Pahang Al‑Sultan Abdullah (UMPSA) organised the PIE‑WiSE 7 Colloquium: Talent, Technology and Transnational Pathways, aimed at strengthening international collaboration in STEM education, technology, and innovation.

The programme brought together representatives from universities, industry partners, and international organisations, including Cardiff Metropolitan University, British Council Malaysia, and TalentCorp Malaysia. The colloquium served as a platform for sharing experiences and expanding strategic partnerships in the development of future technology talent.

The event commenced with a Welcome Address by the Dean of the Faculty of Electrical and Electronic Engineering Technology, Professor Ts. Dr. Hamzah Ahmad, who highlighted the importance of global collaboration in advancing technology education and fostering innovation.

This was followed by a Strategic Address by the Vice‑Chancellor of UMPSA, Professor Ts. Dr. Yatimah Binti Alias, who outlined the university’s vision for expanding international partnerships and strengthening the digital innovation and artificial intelligence (AI) ecosystem in line with future industry demands.

During the keynote sharing session, Professor Dr. Esyin Chew from Cardiff Metropolitan University presented the journey and impact of the PIE‑WiSE collaboration, which has opened avenues for joint research, talent development, and technological innovation between institutions in Malaysia and the United Kingdom.

In her presentation, Professor Dr. Esyin Chew also expressed hopes to further strengthen collaboration between UMPSA and Cardiff Metropolitan University through the implementation of a Dual PhD programme, enabling students to undertake one year of study in the United Kingdom and two years in Malaysia. This initiative is expected to enhance academic mobility, strengthen joint research efforts, and broaden global exposure for postgraduate students.

“Through this initiative, students will not only gain international research exposure but also build global academic networks that will contribute significantly to future technological development,” she said.

Meanwhile, Ms. Prabha Subramaniam, representing British Council Malaysia, shared insights on strengthening UK–Malaysia collaboration through the PIE‑WiSE initiative, which supports the development of high‑impact education and research.

The programme also featured a sharing session by Universiti Malaya, focusing on best practices in building sustainable global partnerships. The session was delivered by Professor Dr. Nazirah Binti Hasnan, Director and Consultant Rehabilitation Medicine Specialist at Universiti Malaya Medical Centre (UMMC), and Professor Dr. Yvonne Lim Ai Lian, Deputy Vice‑Chancellor (Academic and International) of Universiti Malaya. Their presentations provided insights into Universiti Malaya’s experience in developing sustainable international collaborations that support academic and research excellence.

Project DiME (Digital Making and AI Education Initiative), a strategic collaboration between UMPSA STEM Lab and TalentCorp is aimed at developing future-ready digital talent. The initiative focuses on hands-on digital making and artificial intelligence workshops, with particular emphasis on AI applications and semiconductor-related skills, aligning with national talent development priorities. Through Project DiME, TalentCorp actively engages Malaysian diaspora experts based overseas to contribute their industrial and research expertise, providing participants with exposure to global best practices and emerging technologies. The collaboration seeks to enhance practical skill development, strengthen the digital innovation ecosystem, and prepare students and young professionals for careers in high-impact technology sectors.

Week 1 – BHE3233 BTS443 – Digital System Design – Introduction to FPGA Design

Welcome to Week 1 of BHE3233 Digital System Design and BTE4433 Electronic System Design!
Whether you are aiming to master the intricacies of digital logic or build complex electronic systems, this semester will take you on a journey from writing abstract code to deploying robust, optimized physical hardware.
To kick things off, let’s take a bird’s-eye view of the entire course roadmap (Modules 1, 2, and 3), and then dive into the core topics covered this week in Chapter 1: Introduction to IC Design and HDL Environment.
The Course Roadmap: What to Expect This Semester
Our curriculum is structured into three progressive modules that mirror the industry-standard FPGA design workflow:
      1. Module 1: Fundamentals of IC and HDL Design This module lays the groundwork.
        • You will explore the digital design abstraction hierarchy—from behavioral down to physical implementation levels.
        • You will be introduced to Hardware Description Languages (HDL), specifically Verilog, learning its syntax and various modeling styles (structural, dataflow, and behavioral).
        • Most importantly, you will learn how to verify your digital circuits before touching any hardware by constructing testbenches and performing functional simulations using ModelSim.
      2. Module 2: RTL Design and Synthesis Once you know how to write and simulate Verilog, Module 2 focuses on transformation.
        • You will learn how Register Transfer Level (RTL) designs are synthesized into actual hardware components.
        • We will explore technology mapping and gate-level netlist generation using Intel Quartus Prime tools, teaching you how to analyze compilation reports and evaluate resource utilization.
      3. Module 3: Timing Analysis and Design Optimization Synthesizing code into gates is only half the battle; the hardware must also run at the correct speed.
        • This final module emphasizes practical hardware deployment on the Altera DE10-Lite FPGA board.
        • You will dive into Static Timing Analysis (STA), learning about critical paths, setup and hold times, and slack.
        • You will also apply optimization techniques like pipelining to hit timing closure before presenting your final capstone project.

Week 1 Deep Dive: Chapter 1 Overview

This week, we begin with Chapter 1: Introduction to IC Design and HDL Environment, which sets the stage for everything you will build.
    1. The Evolution of Logic Devices
      • Before modern FPGAs (Field-Programmable Gate Arrays) dominated the market, engineers relied on older programmable logic devices.
      • We start by gaining a historical perspective on the evolution from early PLAs (Programmable Logic Arrays), PALs (Programmable Array Logic), and PLDs (Programmable Logic Devices) to the highly advanced FPGA systems we use today.   
    2. FPGAs vs. Microcontrollers vs. ASICs
      • Why use an FPGA? We compare FPGAs against standard Microcontrollers (MCUs) and Application-Specific Integrated Circuits (ASICs).
        1. Microcontrollers execute instructions sequentially and have fixed architectures, making them great for embedded control but slower for massive computations.
        2. ASICs are highly optimized for specific tasks and boast high performance, but they are expensive to develop and their hardware cannot be changed once fabricated.
        3. FPGAs offer the best of both worlds: they provide high parallel processing power and are highly reconfigurable, meaning you can reprogram their internal logic to suit different designs at a moderate cost.

 

3. Design Abstraction Levels

Modern digital design is too complex to build gate-by-gate. Instead, we use different abstraction levels to manage complexity:

      • Behavioral Modeling

Describes the algorithm or behavior using high-level programming constructs (like if-else and case statements).

      • Dataflow Modeling

Describes how data moves through the circuit using Boolean expressions and continuous assignments.

      • Structural Modeling (Gate-Level)

Explicitly describes how individual components and logic gates are wired together physically.

4. The FPGA Design Flow

Bringing a digital concept to life requires a strict engineering workflow. This week, we cover the general steps you will repeat throughout the semester:

      1. Design Entry
        • Writing your Verilog HDL code to describe the circuit.
      2. Synthesis
        • The Quartus software translates your high-level HDL into a gate-level netlist, optimizing the logic and mapping it to the FPGA’s specific resources (like Look-Up Tables and Flip-Flops).
      3. Implementation
        • The software physically places the logic blocks on the FPGA chip and routes the microscopic wires between them.
      4. Timing Analysis
        • Checking to ensure the physical routing delays don’t violate strict timing rules (setup and hold times).
      5. Bitstream Generation
        • Generating a .sof binary configuration file that gets downloaded to the FPGA to physically program it.

5. Our Hardware and Software Environment

To accomplish all of this, we will be getting hands-on with industry-standard tools:

      1. The Hardware
        • The DE10-Lite Development Board, powered by an Intel MAX 10 FPGA. It comes packed with switches, LEDs, 7-segment displays, and plenty of I/O for our projects.
      2. The Software
        • You will learn to navigate Intel Quartus Prime Lite Edition for compiling and synthesizing your code, alongside ModelSim for running your vital pre-hardware functional simulations.

 

Take time this week to install Quartus Prime and ModelSim, familiarize yourself with the software interfaces, and review the DE10-Lite board documentation.Next week, we will start writing real Verilog HDL code and designing our first digital circuits!

Learning from Practice – Reflections on a Sharing Session with Prof Hilman

I recently attended a sharing session by Prof Hilman on research and teaching technology in Electronic Engineering, and it left a strong impression, particularly in terms of how much care and thought he puts into his teaching.

What stood out most was Prof Hilman’s creativity and long-term commitment to his classroom. Over the years, he has developed a series of learning kits that are used across different levels of the programme, from first year right up to final year. These kits are not one-size-fits-all; instead, they are modular, covering topics ranging from analog electronics and RF to sensor design. You can clearly see that they were built with progression in mind, allowing students to grow into the complexity of the subject rather than being overwhelmed by it.

Having developed teaching kits myself, mainly for mini robotics, embedded systems, and IoT, I found myself very much on the same page. Designing kits for teaching is rewarding, but it also comes with its own set of challenges, especially when it comes to deciding how much to give students and how much to leave for them to figure out on their own.

When I talk about “giving everything,” I’m referring to situations where kits / modules that are highly prepared: dedicated PCBs, predefined functional blocks, and ready-to-use modules. This certainly helps students get started more quickly and reduces frustration. At the same time, we sometimes forget that designing those things, like laying out a PCB or deciding how a circuit or functions (in software programming) should be structured, is also an important part of learning.

On the other end of the spectrum is giving students only the bare minimum and expecting them to build everything from scratch. While this can be very powerful for learning, it is not always easy to manage in a real classroom. Students learn at different speeds, and ensuring that everyone can keep up within a fixed semester timeline can be quite challenging.

This is something I’ve often thought about through the lens of the white‑box versus black‑box approach, which I also discussed in my earlier works on tiered scaffolding approaches in Python Slider Game and the STEMCube platform. Both approaches have their place, and the real question is how to strike the right balance.

During the session, I raised this question with Prof Hilman, and we had a good discussion around it. What I found particularly insightful was his view that modularity helps bridge the gap between these two extremes. By designing kits in modules, we can decide which parts are “given” and which parts students are encouraged to develop themselves. As students progress, more of the system can be opened up to them. This makes the learning process more flexible and helps accommodate different learning paces within the same class.

We also touched briefly on the role of AI in analog design, especially during the early design and optimisation stages. While still an evolving area, it sparked an interesting discussion about how such tools might eventually support both teaching and research in electronics engineering.

Overall, the session was a good reminder that effective teaching innovation doesn’t come from choosing one extreme over another, but from carefully designing learning experiences that evolve with students. Prof Hilman’s modular approach is a practical example of how this balance can be achieved, and it’s certainly something I will continue to reflect on in my own teaching practice.

Nurul – March 9th