Category: Information

This week, we continued our exploration of combinatorial circuits, focusing on Lab 3 (Session 5): Implementation and Comparison of Ripple Carry Adder (RCA) and Carry Look-Ahead Adder (CLA). This lab builds on students’ foundational understanding of digital logic and provides hands-on experience with adder architectures that are central to arithmetic logic units (ALUs).

This week is important as we move from theoretical concepts to hands-on hardware implementation. You will be tackling Pre-Labs (Sessions 1 & 2) and Labs 1 & 2 (Sessions 3 & 4).

To succeed in this course and meet our core learning outcomes—specifically CO3, which focuses on developing FPGA designs using industry best practices—you must follow a structured approach.

Phase 1: The Foundation (Pre-Lab Sessions 1 & 2)

Before touching the hardware, you must set up your digital environment. These sessions focus on Project Setup and Functional Verification.

• • • Software Installation: Ensure you have Intel Quartus Prime Lite Edition (Version 18.1) and ModelSim installed on your computer.

      

    • Project Creation: Launch the New Project Wizard in Quartus. Critical step: You must target the specific FPGA device on our board: MAX 10 – 10M50DAF484C7G.

• • • Functional Simulation: Use ModelSim to verify your logic before synthesis. This allows you to catch bugs in a software environment where signals are easy to trace.

Phase 2: Hands-On Implementation (Labs 1 & 2)

Now, it’s time to bring your code to life on the DE10-Lite FPGA Board.

Lab 1: Blinking LEDs (Session 3)

In this lab, you will learn to control the board’s ten user-defined LEDs.

• • • The Logic: You will write a Verilog module utilizing a counter to create a delay.

    • Key Tip: Remember that the onboard clock runs at 50 MHz. Your counter must be large enough (at least 25 bits) to create a blink visible to the human eye.

Lab 2: Switch Inputs and Debouncing (Session 4)

Mechanical switches are “noisy.” When you flip a switch, the signal “bounces” rapidly between high and low before settling.

• The Challenge: You will implement Debounce Logic using a counter to ensure the FPGA only registers a clean, stable signal.

• The Goal: Observe the difference between a direct switch-to-LED connection and one filtered through your debounce logic.

  How to Complete Your Lab Answer Sheets

Your lab worksheet is your evidence of learning. To receive full marks and satisfy CO3 requirements, every session entry must include:

1. Unique Module Naming: To ensure individual work, you must prefix your top-level modules with your unique initials (e.g., AZ_LED_Blinking). Generic names will result in mark deductions.

2. Verilog Code Snippets: Paste snapshots of your design module and your testbench.

3. Simulation Waveforms: Provide ModelSim screenshots. Don’t just paste the image; add notes explaining the logic proof and calculating the clock cycles or frequency observed.

4. Implementation Reports: After compiling in Quartus, open the Compilation Report. You must include snapshots showing Resource Utilization (how many LUTs and Registers your design used).

   Final Submission Reminder

Once you have completed all activities and filled out your worksheet for Sessions 1 through 4:

1. Verify that all dates are recorded correctly.

2. Ensure every module name is unique to you / your team member.

3. Upload the completed document to KALAM (after Lab 6 – Session 8).

Success in digital design comes from attention to detail. Double-check your pin assignments in the Pin Planner before programming, and always verify your timing slack in the Summary Report.

For those who are interested to explore more about Pin Planner, do explore this YouTube :-

Happy designing, engineers!

Welcome to Week 4 of BHE 3233 and BTE4433. This week marks an important step in your journey as electrical and electronic engineering students, as you begin connecting theoretical concepts with actual hardware implementation. You have now moved beyond just understanding logic on paper—you are starting to build and test real digital systems using Verilog and FPGA tools.

We began the week with a refresher on binary operations, which form the foundation of all digital systems. Understanding how numbers are represented and manipulated in binary is essential, as every digital circuit ultimately operates on combinations of 0s and 1s. From there, we transitioned into describing combinatorial logic using Verilog, focusing specifically on adders.

You were first introduced to the half adder, a simple circuit that takes two binary inputs and produces a sum and a carry output. Although basic, it is an important building block in digital design. We then extended this concept to the full adder, which includes a carry-in input, allowing multiple adders to be connected together. This idea of chaining adders is fundamental in designing circuits capable of handling multi-bit arithmetic operations.

To give you a broader perspective, we briefly explored more advanced adder designs such as the ripple carry adder and the carry look-ahead adder. The ripple carry adder is straightforward but can be slow because each carry must propagate through every stage. In contrast, the carry look-ahead adder improves speed by predicting carry signals in advance, although it comes with increased design complexity. These concepts will become more meaningful as you encounter larger and faster digital systems in the future.

Before moving into Lab 1, we started with Lab 0, which focused on simulation. In this lab, you worked with two files: number.v and number_tb.v. The goal was to simulate your design using ModelSim and observe how digital signals behave over time. This is a critical step in digital design, as simulation allows you to verify correctness before implementing your code on actual hardware.

In number.v, you were given a basic up-counter design capable of driving a 7-segment display on the FPGA board. Through this, you explored several important Verilog concepts, including top module declaration, the use of wire data types, and bit buses for representing multi-bit signals. You also examined conditional statements such as if-else, as well as basic mathematical operations within Verilog. By analyzing the waveform output in ModelSim, you were able to see how signals change over time and how your design behaves in response to different inputs. This helped build your understanding of timing and signal relationships in digital circuits.

During the Lab 1, which focused on implementing a running LED design on the DE10-Lite FPGA Board. The task required you to write Verilog code, compile it, assign the correct pins for the 10 LEDs on the board, and program the FPGA. The result was a sequence of LEDs lighting up from one end of the board to the other, demonstrating a simple but effective hardware implementation of your design.

This lab was significant because it introduced you to the complete FPGA workflow, from coding to physical output. Many of you experienced the process of compiling your design, resolving errors, performing pin assignments, and finally observing your design working on actual hardware. This transition from simulation to real-world implementation is a key milestone in your learning.

Thank you Lim for the video shot.

Some common challenges were observed during the session, particularly issues with the hardware not being recognized by your computer. In most cases, this was due to problems with the USB-Blaster driver installation. Ensuring that the driver is properly installed and that the device is correctly detected by the system is crucial. Checking the device manager, trying different USB ports, or reinstalling the driver can often resolve these issues.

Overall, this week has equipped you with essential skills in designing combinatorial circuits using Verilog and implementing them on an FPGA platform. You should now have a clearer understanding of how basic arithmetic circuits are built and how digital designs move from code to hardware.

As we move forward, make sure you are comfortable with both your Verilog coding and FPGA setup. The concepts and skills from this week will serve as the foundation for more advanced topics in the coming weeks. If you are still facing issues, especially with hardware setup, it is important to address them early.

See you in Week 5.

Welcome to Week 2 of BHE 3233. This week, we began exploring one of the most important tools in digital design—Hardware Description Language (HDL). Unlike traditional programming languages, HDL is used to describe hardware behavior and structure, allowing us to design, simulate, and eventually implement digital systems on hardware such as FPGAs.

We focused on Verilog, one of the most widely used HDLs in industry. The goal this week was to familiarize you with the basic syntax and structure of Verilog code. You learned how a typical Verilog module is written, starting with the module declaration, defining inputs and outputs, and ending with the endmodule keyword. Understanding this structure is essential, as every design you create will follow this format.

We also explored key syntax elements in Verilog. This included the use of data types such as wire and reg, which are used to represent connections and stored values in a circuit. You were introduced to basic operators, including logical, relational, and arithmetic operators, which allow you to describe how signals interact. Additionally, we discussed procedural blocks such as always and initial, as well as conditional statements like if-else, which enable you to define how your circuit behaves under different conditions.

Another important concept covered this week was the idea of combinational versus sequential logic in Verilog. While we will go deeper into these topics later, it is important to recognize how Verilog can be used to represent both types of circuits through different coding styles.

A major highlight of the week was the introduction to the testbench. A testbench is a separate Verilog module used to simulate and verify your design. Instead of implementing your code directly on hardware, a testbench allows you to apply input stimuli and observe the output in a controlled environment. This helps you identify errors early and ensures that your design behaves as expected.

In your testbench files, you learned how to declare signals, instantiate your design module, and apply different input combinations over time. You also explored how simulation tools display outputs in the form of waveforms, which provide a visual representation of signal changes. This is a critical skill, as simulation and verification are essential steps in any digital design workflow.

Overall, Week 2 laid the foundation for everything that follows in this course. You now have a basic understanding of how to write Verilog code and how to test your designs using a testbench. These skills will be used extensively in the coming weeks as we move into more complex digital circuits and FPGA implementation.

As you continue practicing, focus on writing clean and correct syntax, and always verify your designs using a testbench before moving forward. This habit will save you a lot of time and help you become a more effective digital designer.

See you in next week!

Week 1 Deep Dive: Chapter 1 Overview

Take time this week to install Quartus Prime and ModelSim, familiarize yourself with the software interfaces, and review the DE10-Lite board documentation.Next week, we will start writing real Verilog HDL code and designing our first digital circuits!