Category: Information

Hi everyone,

After successfully navigating code comprehension and hardware debugging in Stages 1 and 2, our journey through digital system design enters its most advanced phases. This week, we focused on Stage 3: Semi-Completed Programming and Stage 4: New Programming Task (Comparative Optimization).

These stages push us beyond merely “making it work” to actually architecting complete systems and evaluating trade-offs like true digital design engineers. Here is a breakdown of our milestones and the core learning outcomes for each project.

Stage 3: Semi-Completed Programming (Architectural Completion)

In Stage 3, we took foundational components and integrated them into complete, functioning architectures.

Project 1: AES Cryptography (The Logic-Optimized S-Box)

• • The Challenge: Transitioning away from a memory-heavy Look-Up Table (LUT) to a logic-optimized approach using Galois Field (GF(2)) composite arithmetic. We had to complete the missing Boolean equations for multiplicative inversion.
    

• • Learning Outcome: Mastering Mathematical Hardware. We learned how complex cryptography math (like Galois Fields) is synthesized into pure Boolean logic (XOR, AND, OR gates), demonstrating how a “calculation” approach saves memory at the cost of logic depth.
    

Project 2: The Multiplier (Pipelining for Speed)

• • The Challenge: We upgraded a combinational multiplier by inserting registers into the middle of the logic “fences” to create a Pipelined Multiplier.
    
  • Learning Outcome: Increasing Throughput. By breaking a long combinational path into smaller stages, we learned how pipelining allows a new multiplication to start every clock cycle, drastically increasing the system’s Max Frequency (fmax)

Project 3: FIR Filter (Structural Integration)

• • The Challenge: We integrated our verified Multiply-Accumulate (MAC) units and Delay Lines to build a complete Direct Form FIR Filter.
  • Learning Outcome: Preventing Arithmetic Overflow. The crucial lesson here was calculating exact bit-widths for signal growth. We learned that multiplying two 4-bit inputs yields an 8-bit output, and accumulating three of these 8-bit partial products requires a 10-bit final output to prevent overflow.

Project 4: UART Controller (The Transmitter FSM)

• • The Challenge: Wrapping raw serial data into a standardized UART frame by building a Finite State Machine (FSM) that transitions through IDLE, START, DATA, and STOP states based on precise “ticks” from our Baud Rate Generator.
    
  • Learning Outcome: Protocol Synchronization. We learned how to reliably sequence hardware operations using FSMs, ensuring that communication lines are held HIGH during idle and strictly synchronized to a predetermined baud rate for data integrity.

Moving on

Stage 4: Comparative Optimization (New Programming Tasks)

Stage 4 is where engineering design trade-offs shine. We escalated our designs and used Quartus tools (like the Timing Analyzer and Resource utilization reports) to scientifically compare competing architectures.

Project 1: AES Cryptography (LUT vs. Logic Trade-offs)

• • The Challenge: We integrated both the Stage 1 (Table-based) and Stage 3 (Logic-based) architectures onto the DE10-Lite FPGA, using a hardware switch to “toggle” between them.
    
  • Learning Outcome: Resource vs. Speed Optimization. By running a Static Timing Analysis (STA), we learned to scientifically deduce which architecture to use depending on the application—evaluating why a LUT is better for a high-speed cryptographic processor while Boolean logic is superior for a low-area IoT device.
    

Project 2: The Multiplier (16-bit Escalation)

• • The Challenge: We escalated our multiplier from 4-bit to 16-bit and compared all three architectures: Behavioral, Sequential, and Pipelined.
    
  • Learning Outcome: Evaluating Complex Architectural Trade-offs. We learned how expanding bit-widths exponentially deepens the logic tree. The outcome was understanding how to choose an architecture based on strict constraints (e.g., choosing sequential for space-constrained handhelds vs. pipelined for high-performance CPU ALUs).
    

Project 3: FIR Filter (Direct vs. Transposed Form)

• • The Challenge: We redesigned our filter into the Transposed Form, a mathematically identical structure that places delay registers between the adders rather than at the input.
    
  • Learning Outcome: Shortening the Critical Path. We learned a major DSP optimization technique: by separating combinational adders with registers, we shortened the critical path delay. Even though this uses slightly more Logic Elements, it dramatically boosts the f max making it ideal for high-speed audio/sensor processing.

Project 4: UART Controller (FSM Encoding & Parity)

• • The Challenge: We expanded the UART to 16-bit with Even Parity error checking and compared two FSM architectures: Binary Encoding versus One-Hot Encoding.
    
  • Learning Outcome: FSM Encoding Trade-offs. We gained hands-on experience in how the Quartus compiler assigns flip-flops. We discovered that Binary Encoding saves area (fewer flip-flops) but requires heavier decoding logic, whereas One-Hot Encoding uses more flip-flops but simplifies decoding, resulting in better setup slack and a faster maximum frequency.

This week in the lab, we move forward in our hardware design journey by executing Stage 1: Workout Programming and Stage 2: Debugging Specific Malfunctions across four highly distinct FPGA projects. These stages forced us to transition from merely reading code to actively troubleshooting real-world hardware logic errors.

Completion of Stage 1 & 2 activities

1. 1. 1. 1. The State Register: This is a synchronous block (using always @(posedge clk)) that updates the current state to the next state at every clock edge, or resets it when a reset signal is triggered.
         2. The Next-State Logic: A combinational block that evaluates the current state and external inputs to determine what the next state should be.
         3. The Output Logic: A combinational block that generates the output signals based on the current state (Moore machine) or both the current state and inputs (Mealy machine).

1. 1. 1. 1. S0: Nothing matched yet.
         2. S1: Matched “1”.
         3. S2: Matched “10”
         4. S3: Matched “101”
         5. S4: Matched the full “1011” sequence (this is where the output goes high).

1. 1. 1. IDLE: Waiting for the start command.
      2. LINK_ESTABLISH: Attempting the communication handshake.
      3. DATA_TRANSFER: The active data transmission session
      4. LINK_TERMINATE: Securely closing the session 

The book is finally in =).

There is a specific kind of satisfaction in hardware engineering—the moment a conceptual logic circuit transitions from a schematic to a functional physical implementation. My fascination with this process began in 1999 during my undergraduate studies under Professor Othman Sidek. Back then, the ability of an FPGA to house a vast array of logic functions felt revolutionary.

It all started with a project in my Digital Electronics 2 subject. I remember it vividly, we built an automated counter for badminton matches. The digital logic system was designed to detect whether a shuttlecock landed in or out of bounds to assist the umpire in ruling points. That small-scale project served as the gateway to a much deeper exploration into digital systems.

From Undergraduate Roots to GSM Architecture

By the time I reached my final year project, I was diving deep into digital systems for GSM communication modules. Through a family connection—my cousin, who was then a technician for a leading telecommunications provider—I gained invaluable access to the industry standards of the time.

I was particularly focused on implementing Convolutional Encoders, which were essential for error correction in mobile networks. At the time, we worked across the five primary channel types:

1. 1. 1. TCH/FS (Full Rate Speech)

      2. TCH/HS (Half Rate Speech)

      3. FACCH (Fast Associated Control Channel)

      4. SACCH (Slow Associated Control Channel)

      5. SDCCH (Standalone Dedicated Control Channel)

The successful implementation of these designs wasn’t just a hurdle to pass for graduation, it was the foundation of my continued passion with digital logic =p

Fast forward to 2021, I returned to the classroom to teach Digital System Design. Re-engaging with the subject after years in the field felt like a homecoming. During this period, I began supervising Phuah Soon Eu on the project involving the implementation of metaheuristic algorithms on IC chips.

The inherent challenges of translating high-level algorithms into hardware were tackled: managing floating-point arithmetic, optimizing RAM architectures, and modifying algorithmic flows to suit the rigid requirements of digital implementation.

Introducing the Book: A Practical Path for the Novice

Through the project implementation, a persistent “missing link” in technical FPGA education literature. There is a steep cliff between learning basic Verilog and understanding the professional constraints of a production-ready FPGA design.

To bridge this gap, this book is introduced.

Digital System Design with Verilog: FSM, RTL Modelling, Pipelining and Static Timing Analysis

The philosophy is simple: The best way to learn a system is to build it. We designed this text to guide the reader through three critical phases:

1. 1. 1. Foundations: Introduction to FPGA architecture and Hardware Description Language (HDL).

      2. Synthesis: A deep dive into RTL modeling and the complexities of Static Timing Analysis (STA).

      3. Implementation: Mastering FPGA-specific design and the art of optimization.

Moving from Functional to Professional

This book is specifically written for those at the “Novice to Early-Intermediate” stage. It is for the designer to learn to perform a functional simulation but needs to learn how to read synthesis reports, meet specific timing targets, and redesign circuits with objective-driven outcomes.

It has been a privilege to author this with Phuah Soon Eu, and we hope this work serves as a catalyst for the next generation of digital designers—much like a badminton counter did for me decades ago :).