Academia – ESD – Page 6 – Ir. Dr. Nurul Hazlina Noordin

ESD SBEE 3233 – Finite State Machine

January 15th 2021

In the final class of Electronic Systems Design, students were assigned to design a finite state machine module of a sequence detector.

Both designs, verilog module and text fixture, are required before it’s implementation onto FPGAs.

BEE 3233 – ESD SBEE

Today’s class focuses on Verilog Design for Arithmetic Logic Unit.

BEE3233 – Electronic System Design SBEE

Dec 5th, 2020

The class focused on Verilog HDL : Syntax, programming and simulation, for both the design module and testbench.

Students gone through half adder, full adder and 4 bit adder HDL design. Not only is it important for students to be able to describe the circuit using Verilog, the must as well be able to translate the simulated waveform as to verify the functionality of the designed digital module.

SBEE Electronic Systems Design

November 11th, 2020

Third online class of part time course – Electronic System Design, which emphasize on the topic of Arithmetic Logic Unit (ALU) and Finite State Machine (FSM). ALU is a core built of the CPU – that basically made up a computer. Understanding the fundamental of how these units operates digitally plays an important part in developing the competencies for electronic system designers. the topic begins with a simple structure of a half adder and later transits to full adder, ripple carry adder and carry look ahead adder.

The second part of the class focuses on FSM, which elaborates on the two well known concept – Moore and Mealy machines. The concepts of counters and its variabilities were revised and later build up with the two machines mentioned previously.

BEE 3233 – Electronic Systems Design

Another subject that I’ll be facilitating this semester is Electronic System Design.

Learning outcomes of this course are as follows:-

The first outcome is targeted into establishing a solid understanding in design concepts for digital electronics. This include being able to
- Differentiate different digital implementation technologies available – covering from programmable logic arrays, PLD, PAL and FPGAs,
- The concepts of Arithmetic Logic Units – which covers from the basic adders, carry look ahead adders and multipliers, as well as
- Finite state machines and its design techniques
The second outcome aims in developing students ability to design, simulate and implement digital design onto an FPGA. Here, not only is the simulation ability is reflected via
- FPGA programming using Verilog language,
- Implementation of the systems onto an FPGA, as well as
- Analyze and evaluate the performance of the design experimentally
The final outcome touches on a skills that is essential for all engineering graduates – communication both verbal and written skills.Specifically for this course, we’ll look into these two domain:-
- Review journal articles
- Convey engineering design ideas and experimental results via scientific reporting

The knowledge content of this course can be charted out in these 3 main domains:-

Implementation Technologies
- Fixed logic solutions,
- template based
  - The conventional PAL, PLA and CPLD
- Look up table
  - FPGA technologies
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It represents the fundamental building block of the central processing unit (CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In this course, ALU include:-
- Adders
- Multipliers, and
- ALU
And finally, the Finite State Machines. A finite–state machine (FSM), is basically a mathematical model of computation. It is an abstract machine that can be in exactly one of a finite number of states at any given time. Throughout the course, we will look into 3 main concepts in FSM which are:
- mealy
- moore
- mealy moore machine

Intel FPGA – University Program

Participate in a close webinar on implementing FPGA in university curriculum/ programs. Interesting activities and topics, including hands-free platform, which is much needed in this time/situation.