Tag: Academia – ESD

Today’s class covers:-

1. Verilog programming – basics codes and adders
2. Revision on Logic implementation technologies

Today’s topic is on FSM, a way to alleviate the intelligence of a circuit.

https://www.jdoodle.com/execute-verilog-online/

An overview of the course is here

 

All the best everyone.

 

An introduction by FavourIoT.

January 15th 2021

In the final class of Electronic Systems Design, students were assigned to design a finite state machine module of a sequence detector.

Both designs, verilog module and text fixture, are required before it’s implementation onto FPGAs.

Today’s class focuses on Verilog Design for Arithmetic Logic Unit.

 

 

 

Dec 5th, 2020

The class focused on Verilog HDL : Syntax, programming and simulation, for both the design module and testbench.

Students gone through half adder, full adder and 4 bit adder HDL design. Not only is it important for students to be able to describe the circuit using Verilog, the must as well be able to translate the simulated waveform as to verify the functionality of the designed digital module.

November 11th, 2020

Third online class of part time course – Electronic System Design, which emphasize on the topic of Arithmetic Logic Unit (ALU) and Finite State Machine (FSM). ALU is a core built of the CPU – that basically made up a computer. Understanding the fundamental of how these units operates digitally plays an important part in developing the competencies for electronic system designers. the topic begins with a simple structure of a half adder and later transits to full adder, ripple carry adder and carry look ahead adder.

The second part of the class focuses on FSM, which elaborates on the two well known concept – Moore and Mealy machines. The concepts of counters and its variabilities were revised and later build up with the two machines mentioned previously.