Ir. Dr. Nurul Hazlina Noordin

It’s project time =)

This semester in BHE3233 – Digital System Design, we’re exploring practical world of digital hardware by implementing real-time, embedded digital systems using the DE10-Lite FPGA board. Building on the fundamentals of Verilog, FSMs, and RTL design we’ve covered, students now have the opportunity to apply their knowledge through these exciting hands-on projects. Each project emphasizes different aspects of digital design—from FSM sequencing to pipelining and datapath architecture.

These projects were carefully curated to cover a wide range of course outcomes, from combinational and sequential logic design to system-level implementation using FSMs and RTL pipelines. Students not only reinforce theoretical understanding but also gain confidence in developing real-time FPGA applications using Verilog on the DE10-Lite board.

Before jumping into their projects, the students have already completed structured labs covering:-

• • • • FSM design and simulation

      • RTL pipelining

      • Clocking and timing constraints

      • Static timing analysis

      • 7-segment display interfacing

      • Debouncing and switch inputs

These foundational skills are directly applicable to the project implementations.

Here’s a detailed look at the 6 project titles offered this semester:-

1. Morse Code Encoder and LED Blinker

Objective – Design a finite state machine (FSM)-based system that converts input characters (A-Z, 0-9) into Morse code and blinks an LED accordingly.

Key Features –

• • • Input a hardcoded message (or via DIP switches)

    • FSM handles character-to-Morse conversion (dot and dash)

    • LED blinks in Morse timing format

    • Optional – Display current character on a 7-segment display during encoding

Learning Outcomes – FSM design, output timing control, sequential logic, user interaction.

2. Basic 8-bit RISC CPU Implementation

Objective – Build a basic 8-bit CPU that supports core instructions such as ADD, SUB, LOAD, STORE, and JMP.

Key Features –

• 4 to 8 general-purpose registers

• Instruction decoder and ALU unit

• ROM-based instruction memory and RAM-based data storage

• Output status or values via LEDs or 7-segment display

Learning Outcomes – Datapath design, FSM for control unit, memory interfacing, and simple instruction architecture.

3. Parallel Multiplier Using RTL Pipelining

Objective – Design a high-speed 8-bit parallel multiplier using RTL pipelining techniques.

Key Features –

• Inputs via DIP switches or pushbuttons

• Multi-stage pipelining of partial products

• Output result on 7-segment displays

• Compare pipelined design with pure combinational multiplier in terms of:-

  • 1. Critical path delay

    2. Maximum clock frequency

    3. FPGA logic utilization

    4. Throughput

Learning Outcomes – Pipelined architecture, latency vs. throughput, performance analysis.

4. Digital Stopwatch with Lap Function

Objective – Create a stopwatch with basic timing functions and lap time capture.

Key Features:

1. 1. 1. Start/Stop/Reset controls via pushbuttons

      2. FSM-based timing logic

      3. 4-digit multiplexed 7-segment display

      4. Capture and display lap time on button press

Learning Outcomes – Sequential system design, timing counters, 7-segment multiplexing, user interface design.

5. Password-Protected Digital Lock

Objective – Develop a digital locking system with password protection using FSM.

Key Features –

• User password entry via DIP switches

• Status feedback through LEDs or 7-segment

• Lock/unlock logic with real-time comparison

• Optional: Add retry limit and lockout on failed attempts

Learning Outcomes – FSM logic, comparison algorithms using shift registers, and embedded security logic.

6. Dice Game Controller

Objective – Simulate a simple 2-player dice game with visual feedback and turn-based logic.

Key Features –

• Pushbutton to initiate dice roll

• Use LFSR (Linear Feedback Shift Register) to generate pseudo-random numbers (1–6)

• Output displayed using 7-segment or LED

• FSM handles player turns and win conditions

Learning Outcomes – Random number generation using LFSR, FSM game logic, 7-segment display control.

 

Today, each group presented their project progress. Well done!

• Functional demo on the DE10-Lite board

• Timing and performance analysis

• Challenges and solutions in design

Looking forward to final outcome and submission in Kalam!

 

 

Today we look into one of the most critical yet often overlooked topics in FPGA design – Static Timing Analysis (STA). Understanding STA is key to ensuring that your digital design works not only functionally but also reliably at speed. To ground this theoretical topic, students also completed Lab 5, where they compared pipelined and non-pipelined multipliers and analyzed timing and performance parameters.

What Is Static Timing Analysis?

Static Timing Analysis is a method used to determine if a digital circuit will operate correctly at the target clock frequency without needing simulation input vectors. It uses timing constraints and logic paths to compute:

• Setup time

• Hold time

• Propagation delay

• Rise and fall times

• Clock skew

• Critical path delay

• Maximum clock frequency

The goal is to verify that all data signals arrive where they need to, on time, under worst-case conditions.

Key Timing Parameters Explained

To help visualize the concept, we used a simple design involving two D Flip-Flops (FF1 and FF2) connected through a combinational logic block composed of two logic gates.

1. Setup Time

This is the minimum time the data must be stable before the clock edge arrives at FF2. If violated, data may not be correctly latched.

2. Hold Time

The data must remain stable after the clock edge. If violated, metastability may occur.

3. Propagation Delay

This is the time taken for the signal to travel through the logic gates between FF1 and FF2. It’s dependent on the type and number of gates.

4. Rising/Falling Time

The transition period from low to high or high to low in the signal waveform. Faster transitions are better for minimizing timing uncertainty.

5. Clock Skew

This occurs when the clock arrives at FF1 and FF2 at slightly different times. Clock skew can reduce the effective timing margin.

Example in Class Two Flip-Flops and Logic Path

Imagine a logic path between FF1 (source) and FF2 (destination)

Let’s assume-

• Propagation delay through AND = 2ns

• Propagation delay through OR = 3ns

• Setup time of FF2 = 1ns

• Clock skew = 0.5ns

Then, the total delay from FF1 to FF2 is –

To meet setup time, the clock period must be at least:

This gives a maximum clock frequency of:

Lab 5 – Pipelining vs Non-Pipelining in Multiplier Design

In Lab 5, students implemented and tested two versions of a multiplier:

• Non-Pipelined Multiplier – Straightforward, all computation happens in one clock cycle.

• Pipelined Multiplier – Operation split into multiple stages with registers (flip-flops) in between.

They then analyzed the following performance metrics – (hypothetically =))

• Pipelining reduces the critical path delay, allowing the design to run at a much higher clock frequency.

• While pipelining increases the logic utilization (more flip-flops), the throughput improves significantly, making it ideal for high-speed applications like real-time data processing in picosatellites or image processing.

• Static timing analysis helps quantify the improvements, giving insight into real performance beyond just functional correctness.

See you next week for your FPGA project development =)