BHE3233 – Week 12 – Project Development – Ir. Dr. Nurul Hazlina Noordin

It’s project time =)

This semester in BHE3233 – Digital System Design, we’re exploring practical world of digital hardware by implementing real-time, embedded digital systems using the DE10-Lite FPGA board. Building on the fundamentals of Verilog, FSMs, and RTL design we’ve covered, students now have the opportunity to apply their knowledge through these exciting hands-on projects. Each project emphasizes different aspects of digital design—from FSM sequencing to pipelining and datapath architecture.

These projects were carefully curated to cover a wide range of course outcomes, from combinational and sequential logic design to system-level implementation using FSMs and RTL pipelines. Students not only reinforce theoretical understanding but also gain confidence in developing real-time FPGA applications using Verilog on the DE10-Lite board.

Before jumping into their projects, the students have already completed structured labs covering:-

- - - FSM design and simulation
    - RTL pipelining
    - Clocking and timing constraints
    - Static timing analysis
    - 7-segment display interfacing
    - Debouncing and switch inputs

These foundational skills are directly applicable to the project implementations.

Here’s a detailed look at the 6 project titles offered this semester:-

1. Morse Code Encoder and LED Blinker

Objective – Design a finite state machine (FSM)-based system that converts input characters (A-Z, 0-9) into Morse code and blinks an LED accordingly.

Key Features –

- - Input a hardcoded message (or via DIP switches)
  - FSM handles character-to-Morse conversion (dot and dash)
  - LED blinks in Morse timing format
  - Optional – Display current character on a 7-segment display during encoding

Learning Outcomes – FSM design, output timing control, sequential logic, user interaction.

2. Basic 8-bit RISC CPU Implementation

Objective – Build a basic 8-bit CPU that supports core instructions such as ADD, SUB, LOAD, STORE, and JMP.

Key Features –

4 to 8 general-purpose registers
Instruction decoder and ALU unit
ROM-based instruction memory and RAM-based data storage
Output status or values via LEDs or 7-segment display

Learning Outcomes – Datapath design, FSM for control unit, memory interfacing, and simple instruction architecture.

3. Parallel Multiplier Using RTL Pipelining

Objective – Design a high-speed 8-bit parallel multiplier using RTL pipelining techniques.

Key Features –

Inputs via DIP switches or pushbuttons
Multi-stage pipelining of partial products
Output result on 7-segment displays
Compare pipelined design with pure combinational multiplier in terms of:-
- 1. Critical path delay
  2. Maximum clock frequency
  3. FPGA logic utilization
  4. Throughput

Learning Outcomes – Pipelined architecture, latency vs. throughput, performance analysis.

4. Digital Stopwatch with Lap Function

Objective – Create a stopwatch with basic timing functions and lap time capture.

Key Features:

1. 1. Start/Stop/Reset controls via pushbuttons
  2. FSM-based timing logic
  3. 4-digit multiplexed 7-segment display
  4. Capture and display lap time on button press

Learning Outcomes – Sequential system design, timing counters, 7-segment multiplexing, user interface design.

5. Password-Protected Digital Lock

Objective – Develop a digital locking system with password protection using FSM.

Key Features –

User password entry via DIP switches
Status feedback through LEDs or 7-segment
Lock/unlock logic with real-time comparison
Optional: Add retry limit and lockout on failed attempts

Learning Outcomes – FSM logic, comparison algorithms using shift registers, and embedded security logic.

6. Dice Game Controller

Objective – Simulate a simple 2-player dice game with visual feedback and turn-based logic.

Key Features –

Pushbutton to initiate dice roll
Use LFSR (Linear Feedback Shift Register) to generate pseudo-random numbers (1–6)
Output displayed using 7-segment or LED
FSM handles player turns and win conditions

Learning Outcomes – Random number generation using LFSR, FSM game logic, 7-segment display control.

Today, each group presented their project progress. Well done!