Dec 5th, 2020
The class focused on Verilog HDL : Syntax, programming and simulation, for both the design module and testbench.
Students gone through half adder, full adder and 4 bit adder HDL design. Not only is it important for students to be able to describe the circuit using Verilog, the must as well be able to translate the simulated waveform as to verify the functionality of the designed digital module.
