Month: April 2026

Lab Objectives

The key objectives of this lab were to:

• • 1. Design and implement 4-bit Ripple Carry Adders (RCA) and 4-bit Carry Look-Ahead Adders (CLA)
    2. Perform functional verification using selected test vectors
    3. Implement both designs on an FPGA platform
    4. Analyze and compare post-implementation parameters using Quartus post-implementation reports
    5. Introduce basic ALU functionality, focusing on multiplexing using case statements and transitioning toward decoder-based designs

Adder Design and Implementation

Students designed both adders using structural and behavioral modeling approaches in HDL:

• Ripple Carry Adder (RCA):
  A straightforward adder where each full adder waits for the carry from the previous stage. This simplicity comes at the cost of increased propagation delay.
• Carry Look-Ahead Adder (CLA):
  A faster alternative that computes carry signals in parallel using generate and propagate logic, significantly reducing carry propagation delay.

Both designs were synthesized and deployed on the FPGA to observe real hardware performance, not just simulation results.

Functional Testing

During functional testing, several input combinations were validated to ensure correctness:

• • • A = 5 (0101), B = 3 (0011)
      • Result: 8 (1000)
      • Verified correct operation for both RCA and CLA.

• • • A = 15 (1111), B = 1 (0001)
      • Result: 0 with carry-out = 1
      • This test demonstrated carry spill-over, confirming correct handling of overflow conditions.

These cases helped reinforce how carry propagation affects outputs and highlighted the functional equivalence of RCA and CLA despite architectural differences.

 

Post-Implementation Analysis (Quartus)

An important part of this lab was analyzing the post-implementation reports in Quartus.

 

Students were tasked with extracting and comparing the following parameters for both adder implementations:

• • • • Logic Elements (LEs) Used
        How much FPGA hardware is consumed by RCA versus CLA.
      • Combinational Functions
        Insight into the complexity of logic synthesized by the toolchain.
      • Maximum Clock Frequency (Fmax)
        The highest achievable clock rate based on timing constraints.
      • Critical Path Delay
        The longest combinational delay path, which is especially important when comparing RCA and CLA performance.

As expected, the RCA generally exhibited a longer critical path delay due to serial carry propagation, while the CLA achieved a higher maximum clock frequency, demonstrating its advantage in speed-critical designs.

In digital circuits, Fmax (maximum clock frequency) tells us how fast a circuit can run when a clock is used. It depends on the critical path, which is the longest delay through the combinational logic. Signals must be able to travel along this path and settle before the next clock edge arrives. If the critical path is long, the circuit needs a slower clock. In this lab, the RCA has a longer critical path because the carry must pass through each bit one by one, while the CLA reduces delay by calculating carries in parallel.

When checking the Quartus Timing Analysis Report, students noticed that it shows “No Fmax” and “No clock properties to report.” This is normal for this lab. Both the RCA and CLA designs are purely combinational and do not include any clocked elements such as flip-flops or registers. Since there is no clock defined in the design, Quartus cannot calculate Fmax. Fmax is only reported for sequential circuits where data moves from one register to another using a clock. For this reason, Quartus only reports logic usage and combinational delay. Once registers are added in future labs—such as in a registered ALU or datapath—Fmax and full timing information will become available.

To clearly observe the difference in hardware utilization, the total number of logic gates and Configurable Logic Elements (CLEs) used in the system can be analyzed by implementing both a 32-bit Carry Look-Ahead Adder (CLA) and a 32-bit Ripple Carry Adder (RCA). By experimenting with these two adders under identical design conditions, a direct comparison can be made. This allows the differences in resource usage to be clearly identified, where the CLA generally requires more gates and CLEs due to its complex carry logic, while the RCA uses fewer resources but operates with a longer propagation delay.

The example design above employs a genvar as a compile-time counter within a Verilog generate loop to create the 32 stages of the ripple carry adder. The counter variable i controls the instantiation of each full adder, where A[i] and B[i] represent the operand bits at position i, and carry[i] and carry[i+1] form the carry chain between adjacent stages. This approach improves scalability and code modularity, allowing the adder width to be easily adjusted without altering the underlying architecture. Importantly, the use of a counter does not affect the synthesized hardware, as the loop is unrolled during synthesis.

Introduction to Basic ALU Concepts

In the latter part of the lab, we began transitioning from simple adders to basic ALU design concepts:

• • 1. Students implemented a simple ALU capable of performing multiple operations.
    2. A case statement was used to implement a multiplexer that selects the desired operation based on an opcode.
    3. This approach helped students understand how operation selection works internally within an ALU.

We also discussed the next step in this progression: moving from case-based multiplexing toward decoder-based control logic, which scales better for more complex ALU designs.

You can also take this up a level by having your ALU with output assigned to 7 segment display:-

 

Key Takeaways

By the end of this lab, you should be able to:

• • 1. Understand the architectural and performance differences between RCA and CLA
    2. Validate combinational circuits through simulation and FPGA implementation
    3. Interpret FPGA post-implementation reports to justify design trade-offs
    4. See how simple adders evolve into more complex building blocks, such as ALUs

This lab serves as a crucial bridge between basic combinational logic and more advanced processor datapath components, setting the stage for upcoming topics in sequential logic and CPU design.