BHE3233 BTS4433 – Week 7 – Sequential RTL – Lab 4

Welcome to Week 7! This week, we took a massive leap in our digital design journey by exploring Register Transfer Level (RTL) sequential circuits. Unlike combinational circuits, sequential circuits have memory, meaning their outputs depend not only on current inputs but also on previous input
history. At the heart of these sequential designs is the Finite State Machine (FSM).
In digital design, FSMs are used to control system behavior by transitioning between a finite number of states based on inputs and clock cycles.
When we build FSMs in Verilog, we generally divide the architecture into three main blocks:
        1. The State Register: This is a synchronous block (using always @(posedge clk)) that updates the current state to the next state at every clock edge, or resets it when a reset signal is triggered.
        2. The Next-State Logic: A combinational block that evaluates the current state and external inputs to determine what the next state should be.
        3. The Output Logic: A combinational block that generates the output signals based on the current state (Moore machine) or both the current state and inputs (Mealy machine).
In class, we looked at a practical example: a sequence detector acting as a lock that opens whenever the serial bit pattern “1011” is achieved.
Before writing any Verilog code, it is incredibly important to derive your state machine on pen and paper first. Drawing an abstract state diagram ensures your states and transition logic actually make sense.
For the “1011” detector, our state diagram tracks how much of the pattern we have seen so far:
        1. S0: Nothing matched yet.
        2. S1: Matched “1”.
        3. S2: Matched “10”
        4. S3: Matched “101”
        5. S4: Matched the full “1011” sequence (this is where the output goes high).
By mapping out the transition arrows—such as moving from S1 to S2 if the input is 0, or dropping back to S0 if the sequence is broken—you establish the exact mathematical behavior your next-state logic block needs to model.
Hands-On: Lab 4 and the Satellite Communication System
Once we nailed down the state diagrams on paper, we moved into the hardware phase with Lab 4: Finite State Machine for Satellite Communication Link
In real picosatellite systems, communication links require a strict, multi-stage initialization and termination process . You simulated this exact scenario using a four-state FSM:
      1. IDLE: Waiting for the start command.
      2. LINK_ESTABLISH: Attempting the communication handshake.
      3. DATA_TRANSFER: The active data transmission session
      4. LINK_TERMINATE: Securely closing the session 
During the lab, you mapped your DE10-Lite board’s switches to act as the transition triggers (e.g., SW0 to start communication, SW1 to signify link established) and used the LEDs to track which state the FSM was currently in.
By verifying the state transitions in a ModelSim simulation and testing it directly on the physical board, you successfully built a control system identical to those used in real-time embedded space missions !
Keep practicing drawing those state diagrams on paper before jumping into Quartus. See you next week!